| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
lias-logicalimm.s
rm64-leaf-compact-unwind.s
rm64-system-encoding.s
asic-a64-diagnostics.s
asic-a64-instructions.s
ot-req-case-insensitive.s
ot-req-diagnostics.s
ot-req.s
dr-pseudo-obj-errors.s
dr-pseudo.s
it.local.cfg
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
rm64-adr.s
rm64-advsimd.s
rm64-aliases.s
rm64-arithmetic-encoding.s
rm64-arm64-fixup.s
rm64-basic-a64-instructions.s
rm64-be-datalayout.s
rm64-bitfield-encoding.s
rm64-branch-encoding.s
rm64-condbr-without-dots.s
rm64-crypto.s
rm64-diagno-predicate.s
rm64-diags.s
rm64-directive_loh.s
rm64-elf-reloc-condbr.s
rm64-elf-relocs.s
rm64-fp-encoding.s
rm64-large-relocs.s
rm64-leaf-compact-unwind.s
rm64-logical-encoding.s
rm64-mapping-across-sections.s
rm64-mapping-within-section.s
rm64-memory.s
rm64-nv-cond.s
rm64-optional-hash.s
rm64-separator.s
rm64-simd-ldst.s
rm64-small-data-fixups.s
rm64-spsel-sysreg.s
rm64-system-encoding.s
rm64-target-specific-sysreg.s
rm64-tls-modifiers-darwin.s
rm64-tls-relocs.s
rm64-v128_lo-diagnostics.s
rm64-variable-exprs.s
rm64-vector-lists.s
rm64-verbose-vector-case.s
asic-a64-diagnostics.s
asic-a64-instructions.s
lf-globaladdress.ll
lf-reloc-addend.s
lf-reloc-condbr.s
icv3-regs.s
it.local.cfg
eon-2velem.s
eon-3vdiff.s
eon-across.s
eon-compare-instructions.s
eon-crypto.s
eon-diagnostics.s
eon-extract.s
eon-mov.s
eon-perm.s
eon-scalar-compare.s
eon-scalar-dup.s
eon-simd-copy.s
eon-simd-ldst-multi-elem.s
eon-simd-ldst-one-elem.s
eon-simd-misc.s
eon-simd-post-ldst-multi-elem.s
eon-tbl.s
oneon-diagnostics.s
ptional-hash.s
ls-relocs.s
race-regs.s
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
asic-a64-diagnostics.s
asic-a64-instructions.s
eon-compare-instructions.s
eon-diagnostics.s
eon-scalar-fp-compare.s
eon-sxtl.s
eon-uxtl.s
ptional-hash.s
|
| 5f1f4773d95560b68a9c75856563e45e3a4d57e3 |
01-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195803:
------------------------------------------------------------------------
r195803 | mcrosier | 2013-11-26 17:45:58 -0800 (Tue, 26 Nov 2013) | 1 line
[AArch64] Add support for NEON scalar floating-point absolute difference.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195994 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-scalar-abs.s
|
| 2527bdac885f5822bb2b9a805fc9d80b35dd8f8b |
01-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195788:
------------------------------------------------------------------------
r195788 | mcrosier | 2013-11-26 14:17:37 -0800 (Tue, 26 Nov 2013) | 2 lines
[AArch64] Add support for NEON scalar floating-point to integer convert
instructions.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195993 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-scalar-cvt.s
|
| e8bb6e26b83e08631ad336bb0d8076787b858c34 |
25-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195330:
------------------------------------------------------------------------
r195330 | apazos | 2013-11-21 00:16:15 -0800 (Thu, 21 Nov 2013) | 5 lines
Implemented Neon scalar vdup_lane intrinsics.
Fixed scalar dup alias and added test case.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195612 91177308-0d34-0410-b5e6-96231b3b80d8
eon-scalar-dup.s
|
| 36c7806f4eacd676932ba630246f88e0e37b1cd4 |
19-Nov-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-simd-ldst-one-elem.s
|
| 282a979dddff8d06a744c1b686fb3b7a7619d0f4 |
19-Nov-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195072 91177308-0d34-0410-b5e6-96231b3b80d8
eon-3vdiff.s
eon-diagnostics.s
|
| 01dd5728cc897777da95a7f4672b5a2540d52564 |
19-Nov-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Add predicate for AArch64 crypto instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195071 91177308-0d34-0410-b5e6-96231b3b80d8
eon-crypto.s
|
| 69b2447b6a3fcc303e03cba8c7c50d745b0284d2 |
18-Nov-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
[AArch64 NEON]Add mov alias for simd copy instructions.
Set some unspecified bits of INS/DUP to zero as ARMARM requested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194996 91177308-0d34-0410-b5e6-96231b3b80d8
eon-simd-copy.s
|
| 27df434c5e8c78e8b3e6e9596b55a6a6bd8d5116 |
14-Nov-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
Add test case for AArch64 NEON instruction set misc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194673 91177308-0d34-0410-b5e6-96231b3b80d8
eon-simd-misc.s
|
| a08063a000cfc7499f08a472d85f14e7a5e90f8d |
14-Nov-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
Implement aarch64 neon instruction class SIMD misc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194656 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
|
| 082ac99cc86b17c7cd2a1f2a6faa2d1adc184e17 |
14-Nov-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement AArch64 NEON instruction set AdvSIMD (table).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-tbl.s
|
| 13c83a2a09a0842ff57ec020fe3f534de766ccd1 |
12-Nov-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar
copy in MC layer. Added the MC layer tests. Fixed triple setting in test cases.
Patch by Ana Pazos <apazos@codeaurora.org>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8
eon-3vdiff.s
eon-diagnostics.s
eon-scalar-by-elem-mla.s
eon-scalar-by-elem-mul.s
eon-scalar-by-elem-saturating-mla.s
eon-scalar-by-elem-saturating-mul.s
eon-scalar-dup.s
eon-simd-copy.s
eon-simd-shift.s
|
| 30b2a19f3be840da1bc4aefcaabcbddd2e0130fc |
11-Nov-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-scalar-cvt.s
|
| 8458f371b84ee0cd22c4a433059d53ea6e3ec4f4 |
06-Nov-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement AArch64 Neon instruction set Perm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194123 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-perm.s
|
| 258115258f8fe15e9d74b5fb524f90b75bb917d1 |
06-Nov-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement AArch64 Neon instruction set Bitwise Extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-extract.s
|
| 3ff3a8aa7511bede13e836303a083af37fec4f4e |
05-Nov-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194085 91177308-0d34-0410-b5e6-96231b3b80d8
eon-crypto.s
eon-diagnostics.s
|
| 591c2f738a3e12026ff5504a486d54fc21fb3049 |
05-Nov-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-simd-post-ldst-multi-elem.s
|
| 1a035dd6df1d953af57656491eda28ceef9ad4a3 |
31-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193816 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-scalar-cvt.s
|
| f7ba4897302bf930f7ec4682a296ff4cd736a0e3 |
31-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add diagnostic tests for NEON scalar shift immediate instructions (see: r193790).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193798 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
|
| 1d28917dc39f38847f5c69c0a60cd1491430bdad |
31-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar shift immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193790 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-scalar-shift-imm.s
|
| c2884320feebc543d2ce51151d5418dfc18da9e4 |
31-Oct-2013 |
Amara Emerson <amara.emerson@arm.com> |
[AArch64] Make the use of FP instructions optional, but enabled by default.
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
asic-a64-instructions.s
lf-reloc-ldstunsimm.s
nline-asm-modifiers.s
|
| f853a034a1fdccd194da04ca1e2e1aa8bcbd16b4 |
30-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar floating-point compare instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193691 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-scalar-fp-compare.s
|
| 9540074467ca6af4098467261336edbe61f6deea |
28-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193538 91177308-0d34-0410-b5e6-96231b3b80d8
nline-asm-modifiers.s
|
| ade09c7fe7426dca21310911c8ebca17f738342f |
28-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193537 91177308-0d34-0410-b5e6-96231b3b80d8
ump-table.s
|
| e2f60cf7f10d8e732031a519b321e324b5277210 |
28-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193536 91177308-0d34-0410-b5e6-96231b3b80d8
lf-extern.s
|
| 164bd156fc92dc738e5f8dce5da263e1d17211c4 |
28-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Convert a llc -filetype=obj test into a llvm-mc test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193534 91177308-0d34-0410-b5e6-96231b3b80d8
asic-pic.s
|
| c439c205ba304c7ed1c88fb85c2009e49cfbd0c3 |
18-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar extract narrow instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192970 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-scalar-extract-narrow.s
|
| 3b370a2ac433c4abfbfe8f47c63fee0dbcfcc9e6 |
17-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar three register different instruction
class. The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192908 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-scalar-mul.s
|
| dceac4c5a611f26ebcc88c75cc39075c7df2466e |
16-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar negate instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192843 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-scalar-neg.s
|
| a249914462c7b8f0c25b21eca77df264455290ee |
16-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar absolute value instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192842 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-scalar-abs.s
|
| 8225b23c6adcb1be605108425b7eb169b6439b64 |
16-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192806 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-scalar-saturating-add-sub.s
|
| a2cd42a0a7c46d158714c09047a77b7bc1cf9d69 |
16-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar signed saturating accumulated of unsigned
value and unsigned saturating accumulate of signed value instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192800 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-scalar-saturating-add-sub.s
|
| 1824bd0ef84bd162065f9d1fad4c325a39736248 |
15-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar signed saturating absolute value and
scalar signed saturating negate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192733 91177308-0d34-0410-b5e6-96231b3b80d8
eon-scalar-abs.s
eon-scalar-neg.s
|
| 942827b1139c432239648ef54d1df5074eac36ec |
14-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar integer compare instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192596 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-scalar-compare.s
|
| 767f816b926376bd850a62a28d35343ad0559c91 |
11-Oct-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
Implement aarch64 neon instruction set AdvSIMD (copy).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192410 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-simd-copy.s
|
| 6a5a667517160ca1b557002a29d08868ae029451 |
10-Oct-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192361 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-simd-ldst-multi-elem.s
|
| 812ddcc50f8bc3ec6ce115863ff2263815906aaf |
10-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)."
This reverts commit r192352. It broke the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192354 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-simd-ldst-multi-elem.s
|
| d622bef31d11a5a6429fe7fad557c9b111e96f69 |
10-Oct-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192352 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-simd-ldst-multi-elem.s
|
| ccb06ae8f3ef0135d4bddf4f0f61f619c3ce3f1e |
09-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
AArch64: migrate ADRP relaxation test to be llvm-mc only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192281 91177308-0d34-0410-b5e6-96231b3b80d8
drp-relocation.s
|
| c97650079383110d66ab104ee60d03ded2be8e35 |
09-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar floating-point reciprocal estimate,
reciprocal exponent, and reciprocal square root estimate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192242 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-scalar-recip.s
|
| 3dfe644f7b6a560e1991b03d8c419c973ac7ed8d |
08-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar signed/unsigned integer to floating-point
convert instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192231 91177308-0d34-0410-b5e6-96231b3b80d8
eon-scalar-cvt.s
|
| 2aeb4771a6ca0ee253e4836edbab5705203d9bb4 |
07-Oct-2013 |
Chad Rosier <mcrosier@codeaurora.org> |
[AArch64] Add support for NEON scalar arithmetic instructions:
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192107 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-scalar-mul.s
eon-scalar-recip.s
|
| beb6afa84397a27e48a9d72ac1d588bc6fcaf564 |
05-Oct-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement aarch64 neon instruction set AdvSIMD (Across).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192028 91177308-0d34-0410-b5e6-96231b3b80d8
eon-across.s
eon-diagnostics.s
|
| dd518bcc9dd9e4028b2a979ced09edd5b6becd07 |
04-Oct-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement aarch64 neon instruction set AdvSIMD (3V elem).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191944 91177308-0d34-0410-b5e6-96231b3b80d8
eon-2velem.s
eon-diagnostics.s
|
| 477fc628b3c9ce1c970d4a678dd5607b15242cc8 |
24-Sep-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Initial support for Neon scalar instructions.
Patch by Ana Pazos.
1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191263 91177308-0d34-0410-b5e6-96231b3b80d8
eon-add-pairwise.s
eon-add-sub-instructions.s
eon-diagnostics.s
eon-rounding-shift.s
eon-saturating-add-sub.s
eon-saturating-rounding-shift.s
eon-saturating-shift.s
eon-scalar-add-sub.s
eon-scalar-reduce-pairwise.s
eon-scalar-rounding-shift.s
eon-scalar-saturating-add-sub.s
eon-scalar-saturating-rounding-shift.s
eon-scalar-saturating-shift.s
eon-scalar-shift.s
eon-shift.s
|
| e54360be01d1eaccd5ef27f510634927aaa887a4 |
17-Sep-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
Implement 3 AArch64 neon instructions : umov smov ins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190839 91177308-0d34-0410-b5e6-96231b3b80d8
eon-simd-copy.s
|
| 630c5e06d633fad142af4b145ee684e90754700e |
13-Sep-2013 |
Tim Northover <tnorthover@apple.com> |
AArch64: use RegisterOperand for NEON registers.
Previously we modelled VPR128 and VPR64 as essentially identical
register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias"
sub-registers). This model is starting to cause significant problems
for code generation, particularly writing EXTRACT/INSERT_SUBREG
patterns for converting between the two.
The change here switches to classifying VPR64 & VPR128 as
RegisterOperands, which are essentially aliases for RegisterClasses
with different parsing and printing behaviour. This fits almost
exactly with their real status (VPR128 == FPR128 printed strangely,
VPR64 == FPR64 printed strangely).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190665 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mov.s
|
| 959cd8f49bb85c8dfe971eb5a8a648ff41ca8ebd |
09-Sep-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions,
SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190288 91177308-0d34-0410-b5e6-96231b3b80d8
eon-3vdiff.s
eon-diagnostics.s
|
| 19fdc268c316b3b0bdcb2b558449819f4f402d6a |
04-Sep-2013 |
Hao Liu <Hao.Liu@arm.com> |
Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll
and 4 convert instructions:
scvtf,ucvtf,fcvtzs,fcvtzu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189925 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-simd-shift.s
|
| 24ec2e5a72d7fca58f8ae2b3c01501a9927ef04e |
16-Aug-2013 |
Daniel Dunbar <daniel@zuster.org> |
[tests] Cleanup initialization of test suffixes.
- Instead of setting the suffixes in a bunch of places, just set one master
list in the top-level config. We now only modify the suffix list in a few
suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py).
- Aside from removing the need for a bunch of lit.local.cfg files, this enables
4 tests that were inadvertently being skipped (one in
Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and
CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been
XFAILED).
- This commit also fixes a bunch of config files to use config.root instead of
older copy-pasted code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188513 91177308-0d34-0410-b5e6-96231b3b80d8
it.local.cfg
|
| d9767021f83879429e930b068d1d6aef22285b33 |
15-Aug-2013 |
Hao Liu <Hao.Liu@arm.com> |
Clang and AArch64 backend patches to support shll/shl and vmovl instructions and ACLE functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188451 91177308-0d34-0410-b5e6-96231b3b80d8
eon-diagnostics.s
eon-shift-left-long.s
eon-shift.s
|
| 87773c318fcee853fb34a80a10c4347d523bdafb |
01-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
AArch64: add initial NEON support
Patch by Ana Pazos.
- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise
- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic
- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same
- Intial implementation of instruction class:
Scalar Arithmetic
- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.
- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
asic-a64-diagnostics.s
asic-a64-instructions.s
eon-aba-abd.s
eon-add-pairwise.s
eon-add-sub-instructions.s
eon-bitwise-instructions.s
eon-compare-instructions.s
eon-diagnostics.s
eon-facge-facgt.s
eon-frsqrt-frecp.s
eon-halving-add-sub.s
eon-max-min-pairwise.s
eon-max-min.s
eon-mla-mls-instructions.s
eon-mov.s
eon-mul-div-instructions.s
eon-rounding-halving-add.s
eon-rounding-shift.s
eon-saturating-add-sub.s
eon-saturating-rounding-shift.s
eon-saturating-shift.s
eon-shift.s
oneon-diagnostics.s
|
| 73477b9f32da6488f2883f33fd17fa0de61f2bd1 |
03-Jul-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Prefix failing commands with not to make clear they are expected to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185554 91177308-0d34-0410-b5e6-96231b3b80d8
lf-objdump.s
icv3-regs-diagnostics.s
race-regs-diagnostics.s
|
| 7130a9561787cf14d5349d22cde1e0b3a4d5c21d |
23-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
AArch64: fix overzealous NEXTing for Windows testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184667 91177308-0d34-0410-b5e6-96231b3b80d8
ls-relocs.s
|
| 7338de37a802970857079b5a532c5dd50d0a6d5d |
17-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
AArch64: print relocation addends if present on AArch64
llvm-objdump should provide some way of printing out the addends present in the
.rela sections for debugging purposes if nothing else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184072 91177308-0d34-0410-b5e6-96231b3b80d8
lf-reloc-addend.s
|
| 7486d92a6c949a193bb75c0ffa0170eeb2fabb80 |
30-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Change how we iterate over relocations on ELF.
For COFF and MachO, sections semantically have relocations that apply to them.
That is not the case on ELF.
In relocatable objects (.o), a section with relocations in ELF has offsets to
another section where the relocations should be applied.
In dynamic objects and executables, relocations don't have an offset, they have
a virtual address. The section sh_info may or may not point to another section,
but that is not actually used for resolving the relocations.
This patch exposes that in the ObjectFile API. It has the following advantages:
* Most (all?) clients can handle this more efficiently. They will normally walk
all relocations, so doing an effort to iterate in a particular order doesn't
save time.
* llvm-readobj now prints relocations in the same way the native readelf does.
* probably most important, relocations that don't point to any section are now
visible. This is the case of relocations in the rela.dyn section. See the
updated relocation-executable.test for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182908 91177308-0d34-0410-b5e6-96231b3b80d8
lf-globaladdress.ll
lf-reloc-addsubimm.s
lf-reloc-condbr.s
lf-reloc-ldrlit.s
lf-reloc-ldstunsimm.s
lf-reloc-movw.s
lf-reloc-pcreladdressing.s
lf-reloc-tstb.s
lf-reloc-uncondbrimm.s
ls-relocs.s
|
| b6ad2bd51195f7675db0f71c5826a12a2b7090fc |
12-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: use full triple for ELF tests
These tests rely specifically on the names of ELF relocations, let alone any
other detail. There's no way they'd work if LLVM was emitting something else by
default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179376 91177308-0d34-0410-b5e6-96231b3b80d8
lf-globaladdress.ll
lf-objdump.s
lf-reloc-addsubimm.s
lf-reloc-condbr.s
lf-reloc-ldrlit.s
lf-reloc-ldstunsimm.s
lf-reloc-movw.s
lf-reloc-pcreladdressing.s
lf-reloc-tstb.s
lf-reloc-uncondbrimm.s
ls-relocs.s
|
| 15e883787f38b7c424e9de4ec8485ad9e32603b0 |
12-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: remove over-zealous use of CHECK-NEXT
It turns out some platforms (e.g. Windows) lay out their llvm-mc slightly
differently with extra newlines; there was no real reason for the test lines to
be consecutive, so this relaxes the FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179375 91177308-0d34-0410-b5e6-96231b3b80d8
ls-relocs.s
|
| f89da7210b09a0a0f7c9ee216cd54dca03c6b64a |
12-Apr-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Replace coff-/elf-dump with llvm-readobj
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179361 91177308-0d34-0410-b5e6-96231b3b80d8
lf-globaladdress.ll
lf-reloc-addsubimm.s
lf-reloc-condbr.s
lf-reloc-ldrlit.s
lf-reloc-ldstunsimm.s
lf-reloc-movw.s
lf-reloc-pcreladdressing.s
lf-reloc-tstb.s
lf-reloc-uncondbrimm.s
ls-relocs.s
|
| 4385f5dfced4e14bc59dfedb1f75116c0aabbc36 |
03-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: implement ETMv4 trace system registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178637 91177308-0d34-0410-b5e6-96231b3b80d8
race-regs-diagnostics.s
race-regs.s
|
| 42a1b2f0b196633c0327801e810fc98849a00c47 |
28-Mar-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: implement GICv3 system registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178236 91177308-0d34-0410-b5e6-96231b3b80d8
icv3-regs-diagnostics.s
icv3-regs.s
|
| c37aa995e3e55c1bdb17a73c3160edf0426b1a1a |
11-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: Undo change to how test was run
This broke on Windows, presumably due to interleaving of output streams.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174873 91177308-0d34-0410-b5e6-96231b3b80d8
asic-a64-diagnostics.s
|
| b5161863866b64498a7faa20e612c55de4bca6f8 |
11-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Make use of DiagnosticType to provide better AArch64 diagnostics.
This gives a DiagnosticType to all AsmOperands in sight. This replaces all
"invalid operand" diagnostics with something more specific. The messages given
should still be sufficiently vague that they're not usually actively misleading
when LLVM guesses your instruction incorrectly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174871 91177308-0d34-0410-b5e6-96231b3b80d8
asic-a64-diagnostics.s
|
| cbff068398a84ed488b7fdab5fea8e05500d385a |
06-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Add AArch64 CRC32 instructions
These instructions are a late addition to the architecture, and may
yet end up behind an optional attribute, but for now they're available
at all times.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174496 91177308-0d34-0410-b5e6-96231b3b80d8
asic-a64-instructions.s
|
| 9e3b31345f0d17b757e183a8384db92616256926 |
06-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Add icache prefetch operations to AArch64
This adds hints to the various "prfm" instructions so that they can
affect the instruction cache as well as the data cache.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174495 91177308-0d34-0410-b5e6-96231b3b80d8
asic-a64-instructions.s
|
| 7bc8414ee99967cb3a89de663c0510563476aa32 |
01-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Add explicit triples to AArch64 tests
Only Linux is supported at the moment, and other platforms quickly fault. As a
result these tests would fail on non-Linux hosts. It may be worth making the
tests more generic again as more platforms are supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174170 91177308-0d34-0410-b5e6-96231b3b80d8
lf-globaladdress.ll
|
| 72062f5744557e270a38192554c3126ea5f97434 |
31-Jan-2013 |
Tim Northover <Tim.Northover@arm.com> |
Add AArch64 as an experimental target.
This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.
This initial commit should have support for:
+ Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
(except the late addition CRC instructions).
+ CodeGen features required for C++03 and C99.
+ Compilation for the "small" memory model: code+static data <
4GB.
+ Absolute and position-independent code.
+ GNU-style (i.e. "__thread") TLS.
+ Debugging information.
The principal omission, currently, is performance tuning.
This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.
Further reviews would be gratefully received.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
asic-a64-diagnostics.s
asic-a64-instructions.s
lf-globaladdress.ll
lf-objdump.s
lf-reloc-addsubimm.s
lf-reloc-condbr.s
lf-reloc-ldrlit.s
lf-reloc-ldstunsimm.s
lf-reloc-movw.s
lf-reloc-pcreladdressing.s
lf-reloc-tstb.s
lf-reloc-uncondbrimm.s
it.local.cfg
apping-across-sections.s
apping-within-section.s
ls-relocs.s
|