| cdd776d13f799da1aff4b2c9c58a236bee74ea2e |
|
24-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: fix assert on unpredictable POP instruction.
POP instructions are aliased to the ARM LDM variants but have different syntax.
This caused two problems: we tried to access a non-existent operand to annotate
the '!', and the error message didn't make much sense.
With some vigorous hand-waving in the error message both problems can be
fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 01b0e94bb731310e72f66977e4b57cd3f3280ba4 |
|
22-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: provide diagnostics on more writeback LDM/STM instructions
The set of circumstances where the writeback register is allowed to be in the
list of registers is rather baroque, but I think this implements them all on
the assembly parsing side.
For disassembly, we still warn about an ARM-mode LDM even if the architecture
revision is < v7 (the required architecture information isn't available). It's
a silly instruction anyway, so hopefully no-one will mind.
rdar://problem/15223374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193185 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| cf3e4cb29a5fd485f11354060bb7a99e8cfdaf09 |
|
07-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: allow cortex-m0 to use hint instructions
The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have
been ported across to the v6M architecture. Fortunately, v6M seems to sit
nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it
fairly easily.
rdar://problem/15144406
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 20546c697f301cd73b3d32d8e33f8a5ef3f9ff27 |
|
30-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
[ARM] Fix Thumb(-2) diagnostic tests.
Changing the diagnostic message for out of range branch targets in 191686 broke the tests.
The diagnostic message for out of range branch targets was changed to be more consistent with the other diagnostics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| b5523ce1bb50e86942ad5273e3a89872c4d26b73 |
|
05-Sep-2013 |
Richard Barton <richard.barton@arm.com> |
Add AArch32 DCPS{1,2,3} and HLT instructions.
These were pretty straightforward instructions, with some assembly support
required for HLT.
The ARM assembler is keen to split the instruction mnemonic into a
(non-existent) 'H' instruction with the LT condition code. An exception for
HLT is needed.
HLT follows the same rules as BKPT when in IT blocks, so the special BKPT
hadling code has been adapted to handle HLT also.
Regression tests added including diagnostic tests for out of range immediates
and illegal condition codes, as well as negative tests for pre-ARMv8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 428715d4e120e6ef6fc898665607a92f3dd02709 |
|
15-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This fixes three issues related to Thumb literal loads:
1. The offset range for Thumb1 PC relative loads is [0..1020] and not [-1024..1020]
2. Thumb2 PC relative loads may define the PC, so the restriction placed on target register is removed
3. Removes unneeded alias between "ldr.n" and t1LDRpci. ".n" is actually stripped by both tablegen
and the ASM parser, so this alias rule really does nothing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188466 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| e921f323533ee751b3fa34bd00d10fa72096ffd3 |
|
09-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Fix assembling of Thumb2 branch instructions.
The long encoding for Thumb2 unconditional branches is broken.
Additionally, there is no range checking for target operands; as such
for instructions originating in assembly code, only short Thumb encodings
are generated, regardless of the bitsize needed for the offset.
Adding range checking is non trivial due to the representation of Thumb
branch instructions. There is no true difference between conditional and
unconditional branches in terms of operands and syntax - even unconditional
branches have a predicate which is expected to match that of the IT block
they are in. Yet, the encodings and the permitted size of the offset differ.
Due to this, for any mnemonic there are really 4 encodings to choose for.
The problem cannot be handled in the parser alone or by manipulating td files.
Because the parser builds first a set of match candidates and then checks them
one by one, whatever tablegen-only solution might be found will ultimately be
dependent of the parser's evaluation order. What's worse is that due to the fact
that all branches have the same syntax and the same kinds of operands, that
order is governed by the lexicographical ordering of the names of operand
classes...
To circumvent all this, any necessary disambiguation is added to the instruction
validation pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 4f7092176c3d3eaae0ea7af26aec2d77b3e4035f |
|
06-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci,
as pldw does not have a literal variant (i.e. pc relative version)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187804 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 0a552d611efe9d1070aff1d35c7f169dd1ab0be7 |
|
02-May-2012 |
Richard Barton <richard.barton@arm.com> |
Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155983 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| a9cc08f24f61e2663a131d7ac16c329b75162e7b |
|
28-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Thumb add(sp plus register) asm constraints.
Make sure when parsing the Thumb1 sp+register ADD instruction that
the source and destination operands match. In thumb2, just use the
wide encoding if they don't. In Thumb1, issue a diagnostic.
rdar://11219154
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 14ce6fac242228dacc5c08040e544141a96880e5 |
|
25-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: improved assembler diagnostics for missing CPU features.
When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.
rdar://11257547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155499 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| ee10ff89a2934636570cb17b756bf31b2a38aab5 |
|
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for LSR/LSL/ROR(immediate).
More of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 5d0492cfc4521ccb13b4961227b279991a17c393 |
|
28-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ADD/SUB instructions encoding selection outside IT block.
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).
rdar://10348481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143201 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| f8bf43ec99d4410c3e351c76f806208d1204129e |
|
03-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Update test for 141010.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 20ed2e7939d6a8e804a51897c3af4588deb48be2 |
|
01-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for ADD(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 72f39f8436848885176943b0ba985a7171145423 |
|
24-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding support for ADD SP instructions.
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| ec8b866434d530dee5b885e9db8da86db053c9ff |
|
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for SVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138360 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 4c821d800a50251633c206b9fe42c99e12f3f511 |
|
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for STR.
Not including tSTRspi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138347 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 1e84f19337d44c04e74af4fb005550b525ef60e5 |
|
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for STM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138345 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 6dcafc0d0b33bebcac28539257a9a5b250542f6a |
|
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Improve error checking for tPUSH and tPOP register lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 10fd9ad8f33815cdbdc0e2db5860f9c5b1954040 |
|
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix think-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 7260c6a4ea19f5eb94068296c1c8e01a99f17a01 |
|
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assemmbly parsing diagnostic improvements for LDM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138287 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 7a010694209ce46c4f415c0b42c3bc03dc094a5c |
|
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Be more lenient on tied operand matching for MUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 88ae2bc6d53bbf58422ff74729da18a53e155b4a |
|
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for MUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 4ec6e888ec6d12b5255afd685b05c8fee1f7fc73 |
|
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for MOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138076 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 1b7b68f08776dc9553399dc3b4e7ab54e5e596c0 |
|
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LSL(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 93b3eff62322803a520e183fdc294bffd6d99bfa |
|
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDM instruction.
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 37f88c7812e4c284bde325e5af583889b6a80fc5 |
|
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding test for BKPT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 00f5d982057574cf65a4a3f29548ff9fb0ecfbd0 |
|
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for ASR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| 194bd8982936c819a4b14335a4d08f28af8f3d42 |
|
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|
| c2408d3ce5fcd1fd4861772fdbe3b6447836e254 |
|
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add testcase for r137746.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-diagnostics.s
|