| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/test/MC/Mips/mips64-alu-instructions.s
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| 1abf0afdd4d8e9d58518a878f30b9eede81303cc |
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07-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Add definition of instruction "drotr32" (double rotate right plus 32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips64-alu-instructions.s
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| e351865b65e92bea8ceeb32ad757d783d0ecea0f |
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16-May-2013 |
Jack Carter <jack.carter@imgtec.com> |
Mips assembler: Add TwoOperandConstraint definitions
This patch removes alias definition for addiu $rs,$imm
and instead uses the TwoOperandAliasConstraint field in
the ArithLogicI instruction class.
This way all instructions that inherit ArithLogicI class
have the same macro defined.
The usage examples are added to test files.
Patch by Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips64-alu-instructions.s
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| 8d99ec574849ca8266e6491ceafee6c6029692b3 |
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19-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Fix InstAlias of XOR and OR macros. Set EmitAlias flag and change
operand type to uimm16.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179872 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips64-alu-instructions.s
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| ef1762b6a1d3353790bdb415788e7d8963e70372 |
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14-Apr-2013 |
Nico Rieck <nico.rieck@gmail.com> |
Use object file specific section type for initial text section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips64-alu-instructions.s
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| 37ef65b9c1b93c386d13089d9ace6a1cc00e82dc |
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05-Feb-2013 |
Jack Carter <jcarter@mips.com> |
This patch that sets the EmitAlias flag in td files
and enables the instruction printer to print aliased
instructions.
Due to usage of RegisterOperands a change in common
code (utils/TableGen/AsmWriterEmitter.cpp) is required
to get the correct register value if it is a RegisterOperand.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips64-alu-instructions.s
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| c147b678206db510336ee95c3b55dc9c0ff19595 |
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17-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips64-alu-instructions.s
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| 457ee1a12e2c52624af7fdb81cf938f6d8d96572 |
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16-Jan-2013 |
Jack Carter <jcarter@mips.com> |
reverting 172579
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips64-alu-instructions.s
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| 490c7d97737ea7719efcea7321d3cfa3984b0027 |
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16-Jan-2013 |
Jack Carter <jcarter@mips.com> |
Akira,
Hope you are feeling better.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips64-alu-instructions.s
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| ec3199f675b17b12fd779df557c6bff25aa4e862 |
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12-Jan-2013 |
Jack Carter <jcarter@mips.com> |
This patch tackles the problem of parsing Mips
register names in the standalone assembler llvm-mc.
Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.
The problem is resolved by the Mips specific AsmParser
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips64-alu-instructions.s
|