| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 633f98bdfa266871dcd17ab27af1594c6cc31d9e |
|
03-Nov-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
AVX-512: added VPCONFLICT instruction and intrinsics,
added EVEX_KZ to tablegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| c6f7c99809cece8c85e180c1b95e6159d8ea9613 |
|
14-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 017d8a3e23b719ece59f2498582db7f25d65c1b9 |
|
12-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192525 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| c429b5cca1a2710657b746b774e606f10200d89e |
|
12-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Mark some more instructions as CodeGenOnly. Remove filters from the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192522 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| e799dbc4bdfd5f3c7856fbcfe0fac56000401f1f |
|
11-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Remove another unnecessary filter from the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| be5c1fd43fd1cef8a18f41978d147190b50f5510 |
|
10-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 5747f946ec810d22d36260a4b18114d5673fd55f |
|
09-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
More x86 disassembler filtering cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 10c7925d69437e2bd182eb4cc47eb4bdfb3af900 |
|
09-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Remove some old filters from the x86 disassembler table builder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| d55fed16a44366f8d9800197ffa67bbd7189568b |
|
08-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Remove unneeded MMX instruction definition by moving pattern to an equivalent instruction definition and removing the filtering from the disassembler table building.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| b9bc43852ceb74c845d28b96594e1ef4ae41329f |
|
08-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| e778f82a1e33826ab012bb970a406c9acf37349b |
|
07-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 36a9b31b981553350f5cc4adad9917656c20e96e |
|
07-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Add disassembler support for long encodings for INC/DEC in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192086 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 279d28265dccc2a7c56f9ea04917c87dc50c1578 |
|
03-Oct-2013 |
Craig Topper <craig.topper@gmail.com> |
Add XOP disassembler support. Fixes PR13933.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191874 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 1765e74c15c83db437018a3c9efabbeb4ce9cbde |
|
22-Aug-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
AVX-512: Added masked SHIFT commands, more encoding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189005 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| d953bcd4876b86e2d99ebbe87c03b2e41298f115 |
|
28-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Remove use of sprintf added to X86 disassembler tablegen code. Send message with instruction name to errs() instead and use a generic message for the llvm_unreachable. Consistent with other places in this file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| dc8a318f44ba5e4f0edf6a19b54ed68b86410878 |
|
28-Jul-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
fixed compilation issue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187325 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| c18f4efc5dd24adcc653806455fc7ae8508e9c66 |
|
28-Jul-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Added encoding prefixes for KNL instructions (EVEX).
Added 512-bit operands printing.
Added instruction formats for KNL instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 23306deb92e2424165f2145895e21e223c3887eb |
|
18-Jun-2013 |
Stefanus Du Toit <stefanus.du.toit@intel.com> |
Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.
For decoding, keep the current behavior of always decoding these as their REP
versions. In the future, this could be improved to recognize the cases where
these behave as XACQUIRE and XRELEASE and decode them as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184207 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 02d2e612521954b5ff7c1ba6fd53e36bc51e1c48 |
|
11-Apr-2013 |
Michael Liao <michael.liao@intel.com> |
Add CLAC/STAC instruction encoding/decoding support
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 9b3939983fd0103b102c7aec0ed08d1e8bd28214 |
|
25-Mar-2013 |
Dave Zarzycki <zarzycki@apple.com> |
x86 -- add the XTEST instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 12dccaed9c0368f4f5ef4312c32b375c725c9daf |
|
11-Mar-2013 |
Kevin Enderby <enderby@apple.com> |
Fixes disassembler crashes on 2013 Haswell RTM instructions.
rdar://13318048
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176828 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 6c3daabc3ee51a8fcb804e0f110f01e59e0e6d61 |
|
12-Feb-2013 |
Kay Tiong Khoo <kkhoo@perfwizard.com> |
Added 0x0D to 2-byte opcode extension table for prefetch* variants
Fixed decode of existing 3dNow prefetchw instruction
Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174920 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 4ffd89fa4d2788611187d1a534d2ed46adf1702c |
|
04-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Sort the #include lines for utils/...
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| be02a90de17f857ba65bbd8a11653ca1bad30adc |
|
08-Nov-2012 |
Michael Liao <michael.liao@intel.com> |
Add support of RTM from TSX extension
- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 8a312fb3aaec90537d434a5cc41edf566ff80dca |
|
19-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| bf4043768c6726db523f99460645842e5024fc7f |
|
31-Aug-2012 |
Craig Topper <craig.topper@gmail.com> |
Add support for converting llvm.fma to fma4 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 49d86c9eb95bf0233cf749c79f0e10d03f33c58e |
|
30-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 95c929f45c01054d91a6878de22892675dd115cf |
|
30-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove some unnecessary filter checks. They were already covered by IsCodeGenOnly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160950 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 24fd0ddf3136ad7dec6c554f3a97f2d24fe2027f |
|
30-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove check for sub class of X86Inst from filter function since caller guaranteed it. Replace another sub class check with ShouldBeEmitted flag since it was factored in there already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160949 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 50c5c8275e576c2129a4ab6146ca4226dcdfe6fe |
|
30-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Simplify code that filtered certain instructions in two different ways. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 87a9ece154acdf2164094e6b5a47bac48a53aa4d |
|
30-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove check for f256mem from has256BitOperands as nothing depended on it and it isn't the only 256-bit memory type anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160946 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| e6c97ffb0d69125d989acc7e1a62c182096dd4e2 |
|
30-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160945 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 7f76cb6666194d7269bbd6ee0966eacc709dd10a |
|
26-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160775 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 76f63aef5645885a4cf3eb3a7274850ed2ff9a62 |
|
19-Jul-2012 |
Richard Trieu <rtrieu@google.com> |
Move around some enum elements so that lastMRM corrects gets assigned 56, which
is one more that MRM_DF which is 55. Previously, it held value 45, the same
as MRM_D0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 75dc33a60b65bbbf2253b0b916df1d36a4da4237 |
|
18-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 5aba78bd8056dc407bcbce4080ffcd12b13c7342 |
|
12-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Update GATHER instructions to support 2 read-write operands. Patch from myself and Manman Ren.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160110 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 1f7a1b68a07ea6bdf521525a7928f4a8c5216713 |
|
26-Jun-2012 |
Manman Ren <mren@apple.com> |
X86: add GATHER intrinsics (AVX2) in LLVM
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256
Modified Disassembler to handle VSIB addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 1386e9b7b16a8138ae7060c2dbb8b029f7c4fce2 |
|
29-May-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 769bbfd951018f9b36f3d2f0d70a23d81f2d3287 |
|
03-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| faf72ffda3bf83b08769428129ee4755787ee6cf |
|
09-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Fix the x86 disassembler to at least print the lock prefix if it is the first
prefix. Added a FIXME to remind us this still does not work when it is not the
first prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152414 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 930a1ebd929aa0ab4c2610e7f7a721c18dcfe052 |
|
27-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 28a713b20ad17f9a02d4677d8a2fea0edb208418 |
|
19-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Add vmfunc instruction to X86 assembler and disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 9e3d0b335111b2df73984a6cfd9ef1cd5d323872 |
|
18-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 06f554d06ab0f9390d04bcbaabb76f572d940249 |
|
30-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Add disassembler support for VPERMIL2PD and VPERMIL2PS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| e6a3a2990e3f783c906e9db58e55439cb06f9fa5 |
|
30-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Add FMA4 instructions to disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147367 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 787a88ff18b3fe9e8f66eda63544eb10a0c806ef |
|
19-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
Remove some unnecessary filtering checks from X86 disassembler table build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| c8eb880a7fb0958a3a048a82c8558beec11f1209 |
|
07-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
More AVX2 instructions and their intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 75485d6746f8b5b23c17cf6d2364e7e1e0705992 |
|
23-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 RORX instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| ee62e4f6d192ee31d1ad9dd0ba0c41db6663d3c7 |
|
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 PEXTR and PDEP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| b53fa8bf19a51f0c49a9f8b6ede3e2ff3bdfb961 |
|
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 BZHI instruction as well as BMI2 feature detection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| dc479c4a897bb7cc756370cc2051da79b65e7d16 |
|
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 17730847d59c919d97f097d46a3fcba1888e5300 |
|
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 566f233ba64c0bb2773b5717cb18753c7564f4b7 |
|
15-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 54a11176f6a5e07e243f1d87ba19ac3f4681976b |
|
14-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 ANDN instruction. Including instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 29480fd798dc6452948f63825ff41c66f09c2493 |
|
11-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 7ea16b01fad5236cc132cb5fc3e443fcbf70d3b8 |
|
06-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 6744a17dcfb941d9fdd869b9f06e20660e18ff88 |
|
04-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 846a2dcada30a3507a1e9af9eabc2919674e669f |
|
01-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix disassembling of INVEPT and INVVPID to take operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| e1b4a1a07ec79440536e4535721f15de3893cd13 |
|
01-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 4da632e6e09b96db4b3f9202cde4e6ca732001c1 |
|
23-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| a08e255e1e47d732b31262a95a8ba810f85735c4 |
|
14-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 58bbb81764ccd20d06018b407d2698e4f1ad0709 |
|
13-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 038197988bcd7619657633da7116c7292187d4ae |
|
11-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 842f58f9be82e1a0d2751e7982ef3641829acf87 |
|
11-Sep-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 98f213cd60f21437846ce4075c0fe15d7f09a3fd |
|
02-Sep-2011 |
Kevin Enderby <enderby@apple.com> |
Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139014 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 3daa5c29d444a759a0c60656d1aaf2579e5e447c |
|
30-Aug-2011 |
Craig Topper <craig.topper@gmail.com> |
Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138795 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| fff64ca9cfdcb8e2fd2e124fcda1c1053523afc6 |
|
30-Aug-2011 |
Kevin Enderby <enderby@apple.com> |
Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138771 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 05bce0beee87512e52428d4b80f5a8e79a949576 |
|
30-Jul-2011 |
David Greene <greened@obbligato.org> |
Unconstify Inits
Remove const qualifiers from Init references, per Chris' request.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136531 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| f37dd02f7743ebd2424480361f5a7db510495c4f |
|
29-Jul-2011 |
David Greene <greened@obbligato.org> |
[AVX] Constify Inits
Make references to Inits const everywhere. This is the final step
before making them unique.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| c37d4bbf1f33c5e4b1c2f1bf1a6e2cae2ae5603a |
|
28-Jul-2011 |
Kevin Enderby <enderby@apple.com> |
Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored. The others remain unchanged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136287 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 7105259ce8e9fd78ce9fc1b7a9aaab123fb5db64 |
|
16-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| d568b3f55294917d1cc701da14a8a7daeb6563e6 |
|
12-Jul-2011 |
Eric Christopher <echristo@apple.com> |
Revert r134921, 134917, 134908 and 134907. They're causing failures
in multiple buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| d4a9066c93da9a5aab47ca228d82e796fdec70c0 |
|
11-Jul-2011 |
David Greene <greened@obbligato.org> |
[AVX] Make Inits Foldable
Manage Inits in a FoldingSet. This provides several benefits:
- Memory for Inits is properly managed
- Duplicate Inits are folded into Flyweights, saving memory
- It enforces const-correctness, protecting against certain classes
of bugs
The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen. This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 4a8ac8de1ddfeaadb9ff13ce361bfc6435f18028 |
|
04-Apr-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Add support for the VIA PadLock instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| a21e2eae3def2fe39caed861dcb73c76c715569b |
|
15-Mar-2011 |
Sean Callanan <scallanan@apple.com> |
X86 table-generator and disassembler support for the AVX
instruction set. This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures. Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 87ca0e077d91b96a765b3b24cadfa8891026a33a |
|
22-Feb-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement xgetbv and xsetbv.
Patch by Jai Menon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| c266600bec4b5ba0ee93ffdfeaafcab8f1295145 |
|
13-Dec-2010 |
Owen Anderson <resistor@mac.com> |
In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| c240bb0ede0541426254d0e0dc81d891beda4b22 |
|
01-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
factor the operand list (and related fields/operations) out of
CodeGenInstruction into its own helper class. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 529b1a43986265fb399eecd0dcbf9c409d049853 |
|
27-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Added the x86 instruction ud2b (2nd official undefined instruction).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 6aeb2e32b7724e7c4bd878d4c899be917492cb32 |
|
05-Oct-2010 |
Sean Callanan <scallanan@apple.com> |
Fixed the disassembler to handle two new X86
instruction forms. Now the ENTER instruction
disassembles correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115573 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 0488fb649a56b7fc89a5814df5308813f9e5a85d |
|
01-Oct-2010 |
Dale Johannesen <dalej@apple.com> |
Massive rewrite of MMX:
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| b2ef4c1235c846c2503d0796541f4255ef1e13f5 |
|
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add basic avx support to the disassembler, also teach it about ssmem/sdmem
operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115019 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 86097c384f84981494ed9c200ff5763afcd960de |
|
07-Sep-2010 |
Dale Johannesen <dalej@apple.com> |
Add patterns for MMX that use the new intrinsics.
Enable palignr intrinsic.
These may need adjustment for a new VT in due course.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 3472766f9eb7d66f234c390ce1b3a8b76f0ee9ce |
|
12-Jul-2010 |
Duncan Sands <baldrick@free.fr> |
Convert some tab stops into spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 9fc05227a2596c545b845ed9a72673995e49d16b |
|
08-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
Implement the major chunk of PR7195: support for 'callw'
in the integrated assembler. Still some discussion to be
done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| c902a59f4c786a2a047f0b4c964a93108f248915 |
|
12-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)
Introduce the VEX_X field
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105859 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 99405df044f2c584242e711cc9023ec90356da82 |
|
09-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 1087f54ddb70bd2a7ab62608161e4a3f0c345935 |
|
05-Jun-2010 |
Chris Lattner <sabre@nondot.org> |
revert r105521, which is breaking the buildbots with stuff like this:
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 3eca98bb3ab1ec27ab8763298c416d282cdaa261 |
|
05-Jun-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Initial AVX support for some instructions. No patterns matched
yet, only assembly encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 4072886a690a853c57c79a87a6423a7bfe0ce61f |
|
20-May-2010 |
Daniel Dunbar <daniel@zuster.org> |
tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor
it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 1a8b789a4b8290d263c1c75411788ca45bae3230 |
|
06-May-2010 |
Sean Callanan <scallanan@apple.com> |
Eliminated the classification of control registers into %ecr_
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 5edca8162623b742282f5f03b0872ac3469b5bed |
|
07-Apr-2010 |
Sean Callanan <scallanan@apple.com> |
Fixed a bug where the disassembler would allow an immediate
argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter. Now, the
disassembler rejects instructions with out-of-range values
for that immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
|
| 5e81716425dc3373fbc834bfa7936a5c1205579b |
|
14-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Check in tablegen changes to fix disassembler related failures caused by r98465.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
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| 80443f914624098db7088d751efbb8dae7743b76 |
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24-Feb-2010 |
Sean Callanan <scallanan@apple.com> |
Changed the table generator so that the X86
disassembler never recognizes InitReg instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
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| cebe955779b264e1fa0423d2ee854fcde43480d7 |
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13-Feb-2010 |
Sean Callanan <scallanan@apple.com> |
Added the rdtscp instruction to the x86 instruction
tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
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| 95a5a7d57015c21b355a351c2efc6866f89b2f61 |
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13-Feb-2010 |
Sean Callanan <scallanan@apple.com> |
Fixed encodings for invlpg, invept, and invvpid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
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| a599de241041eebc84867ac8e4cb76668cabd236 |
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13-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
remove special cases for vmlaunch, vmresume, vmxoff, and swapgs
fix swapgs to be spelled right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
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| eaca5fa8e6a2cb0f84a635da5f1f0f670776d0a5 |
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13-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
Remove special cases for [LM]FENCE, MONITOR and MWAIT from
encoder and decoder by using new MRM_ forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
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| 9492be8d10d7df8efaf33bcf2eb3ad13d49ddd60 |
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13-Feb-2010 |
Sean Callanan <scallanan@apple.com> |
Reworked the Intel disassembler to support instructions
whose opcodes extend into the ModR/M field using the
Form field of the instruction rather than by special
casing each instruction. Commented out the special
casing of VMCALL, which is the first instruction to use
this special form. While I was in the neighborhood,
added a few comments for people modifying the Intel
disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
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| 0d8db8e0a8492ab2d4bef725ec61b519471b97ec |
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12-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
add a bunch of mod/rm encoding types for fixed mod/rm bytes.
This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
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| a7d479c7bd9723cabdd7c9e1e9a1e6e482f78e7e |
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10-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
Introduce a new CodeGenInstruction::ConstraintInfo class
for representing constraint info semantically instead of
as a c expression that will be blatted out to the .inc
file. Fix X86RecognizableInstr to use this instead of
parsing C code :).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95753 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
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| 7fb35a2fd83f5deadefcb230669b07e1d5b98137 |
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22-Dec-2009 |
Sean Callanan <scallanan@apple.com> |
Fixes to the X86 disassembler:
Made LEA memory operands emit only 4 MCInst operands.
Made the scale operand equal 1 for instructions that have no
SIB byte.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
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| 9e6d1d1f5034347d237941f1bf08fba5c1583cd3 |
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19-Dec-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add missing newlines at EOF (for clang++).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
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| 8ed9f51663bc5533f36ca62e5668ae08e9a1313f |
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19-Dec-2009 |
Sean Callanan <scallanan@apple.com> |
Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit
incarnations), integrated into the MC framework.
The disassembler is table-driven, using a custom TableGen backend to
generate hierarchical tables optimized for fast decode. The disassembler
consumes MemoryObjects and produces arrays of MCInsts, adhering to the
abstract base class MCDisassembler (llvm/MC/MCDisassembler.h).
The disassembler is documented in detail in
- lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime)
- utils/TableGen/DisassemblerEmitter.cpp (table emitter)
You can test the disassembler by running llvm-mc -disassemble for i386
or x86_64 targets. Please let me know if you encounter any problems
with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/X86RecognizableInstr.cpp
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