| 9b4053cabd8bda180b352d2d2047209f6ca5f6e8 |
|
06-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Drop the confusing saturate argument to math instruction setup.
This was ridiculous. We were ignoring the inst->header.saturate flag in the
case of math and only math. On gen4, we would leave inst->header.saturate in
place if it happened to be set, which would end up being applied to the
implicit mov and thus trash the first argument. On gen6, we would overwrite
inst->header.saturate with the saturate flag from the argument, which was not
set appropriately in brw_vec4_emit.cpp, and was only not a bug due to our
incompetence at coalescing saturate moves.
By ripping the argument out and making saturate work just like all the other
brw_eu_emit.c code generation, we can avoid both these classes of bugs.
Fixes piglit fog-modes, and the new specific fs-saturate-exp2 case.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48628
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 33dfdc735e052d9c9b33883350e926d40220b6ac |
|
09-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Make brw_set_saturate() use stdbool.
There was a chance for brw_wm_emit.c to screw up and pass (1 << 4) instead of
1, which would get converted to 0 when stored. Instead, use stdbool which
converts nonzero to true/1 like we want.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 6a27506181b29c8b7eda7bd6cf80689f849e181d |
|
07-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Add support for AVG instruction.
From the Ivy Bridge PRM, Vol4 Part3 p152:
"The avg instruction performs component-wise integer average of
src0 and src1 and stores the results in dst. An integer average
uses integer upward rounding. It is equivalent to increment one to
the addition of src0 and src1 and then apply an arithmetic right
shift to this intermediate value."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 29362875f2613ad87abe7725ce3c56c36d16cf9b |
|
25-Apr-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen6+: Add support for GL_ARB_blend_func_extended.
v2: Add support for gen6, and don't turn it on if blending is
disabled. (fixes GPU hang), and note it in docs/GL3.txt
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 9e9ae280e215988287b0f875c81bc2e146b9f5dd |
|
04-May-2012 |
Eric Anholt <eric@anholt.net> |
Revert "i965/fs: Jump from discard statements to the end of the program when done."
This reverts commit 31866308fcf989df992ace28b5b986c3d3770e90.
Fixes piglit glsl-fs-discard-exit-3 and unigine tropics rendering.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 434fc8bde41f07687ad8941ceba03c4b3e0e75bb |
|
27-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
intel: Add extern "C" declarations to headers
These declarations are necessary to allow C++ code to call C code
without causing unresolved symbols (which would make the driver fail
to load).
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| f78f48b6d2c4034a62ab11a558c95901d2245c4a |
|
02-Apr-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove vestiges of function call support from the old VS backend.
This never worked. brwProgramStringNotify also explicitly rejects
programs that use CAL and RET. So there's no need for this to exist.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 31866308fcf989df992ace28b5b986c3d3770e90 |
|
19-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Jump from discard statements to the end of the program when done.
From the GLSL 1.30 spec:
The discard keyword is only allowed within fragment shaders. It
can be used within a fragment shader to abandon the operation on
the current fragment. This keyword causes the fragment to be
discarded and no updates to any buffers will occur. Control flow
exits the shader, and subsequent implicit or explicit derivatives
are undefined when this control flow is non-uniform (meaning
different fragments within the primitive take different control
paths).
v2: Don't emit the final HALT if no other HALTs were emitted.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 2b28fd6ca603df40a5d02aac4035eced3a1d079a |
|
22-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for the MAD opcode on gen6+.
v2: Fix MRF handling on gen7.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 5f4575d42fdaaf671d4b3cdcf2c733ad9d35d339 |
|
26-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Expose brw_set_sampler_message for use outside brw_eu_emit.c.
brw_SAMPLE is full of complex workarounds for original Broadwater
hardware, and I'd rather avoid all that for my next Ivybridge patch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 3aa3c3f75894ca0eb08087c0ec3dd114eeae4bb7 |
|
21-Dec-2011 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
i965: increase the brw eu instruction store size dynamically
Here is the final patch to enable dynamic eu instruction store size:
increase the brw eu instruction store size dynamically instead of just
allocating it statically with a constant limit. This would fix something
that 'GL_MAX_PROGRAM_INSTRUCTIONS_ARB was 16384 while the driver would
limit it to 10000'.
v2: comments from ken, do not hardcode the eu limit to (1024 * 1024)
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 328e6a5497e54b0e8aed803cf6d2ae9a2a00b2fe |
|
21-Dec-2011 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
i965: get the jmp distance by instruction index
If dynamic instruction store size is enabled, while after the brw_JMPI()
and before the brw_land_fwd_jump() function, the eu instruction store
base address(p->store) may change. Thus, the safe way to reference the
jmp instruction is by index instead of by the instruction address.
v2: comments from Eric, don't change the prototype of brw_JMPI
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 0a17093eaf84696b05d04a45d6d51281f7b2786b |
|
21-Dec-2011 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
i965: let the if_stack just store the instruction index
If dynamic instruction store size is enabled, while after
the brw_IF/ELSE() and before the brw_ENDIF() function, the
eu instruction store base address(p->store) may change.
Thus let if_stack just store the instruction index. This is
somehow more flexible and safe than store the instruction
memory address.
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| f1d89638c02afafbf82ef657cd6ba9965dad6738 |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_CONT/brw_WHILE track if depth in loop.
The codegen backends all had this same tracking, so just do it at the
EU level.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 32118cfe37495738ed5931c6b1a71b8ee2ad189c |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start.
This is a similar cleanup to what we did for brw_IF(), brw_ELSE(),
brw_ENDIF() handling.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 9f8814752f306cb9a26d283f0b7cf876639e10f7 |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop unused do_insn argument from gen6_CONT().
The branch distances get patched up later at the WHILE instruction.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 9308f298300beaa757194a0db8ed50924754c011 |
|
28-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Initial implementation of transform feedback.
This patch adds basic transform feedback capability for Gen6 hardware.
This consists of several related pieces of functionality:
(1) In gen6_sol.c, we set up binding table entries for use by
transform feedback. We use one binding table entry per transform
feedback varying (this allows us to avoid doing pointer arithmetic in
the shader, since we can set up the binding table entries with the
appropriate offsets and surface pitches to place each varying at the
correct address).
(2) In brw_context.c, we advertise the hardware capabilities, which
are as follows:
MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS 64
MAX_TRANSFORM_FEEDBACK_SEPARATE_ATTRIBS 4
MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS 16
OpenGL 3.0 requires these values to be at least 64, 4, and 4,
respectively. The reason we advertise a larger value than required
for MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS is that we have already
set aside 64 binding table entries, so we might as well make them all
available in both separate attribs and interleaved modes.
(3) We set aside a single SVBI ("streamed vertex buffer index") for
use by transform feedback. The hardware supports four independent
SVBI's, but we only need one, since vertices are added to all
transform feedback buffers at the same rate. Note: at the moment this
index is reset to 0 only when the driver is initialized. It needs to
be reset to 0 whenever BeginTransformFeedback() is called, and
otherwise preserved.
(4) In brw_gs_emit.c and brw_gs.c, we modify the geometry shader
program to output transform feedback data as a side effect.
(5) In gen6_gs_state.c, we configure the geometry shader stage to
handle the SVBI pointer correctly.
Note: ordering of vertices is not yet correct for triangle strips
(alternate triangles are improperly oriented). This will be addressed
in a future patch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| d4976158c7f32705b48c773c3abd1b22bebe9c16 |
|
29-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Implement pass-through GS for transform feedback.
In Gen6, transform feedback is accomplished by having the geometry
shader send vertex data to the data port using "Streamed Vertex Buffer
Write" messages, while simultaneously passing vertices through to the
rest of the graphics pipeline (if rendering is enabled).
This patch adds a geometry shader program that simply passes vertices
through to the rest of the graphics pipeline. The rest of transform
feedback functionality will be added in future patches.
To make the new geometry shader easier to test, I've added an
environment variable "INTEL_FORCE_GS". If this environment variable
is enabled, then the pass-through geometry shader will always be used,
regardless of whether transform feedback is in effect.
On my Sandy Bridge laptop, I'm able to enable INTEL_FORCE_GS with no
Piglit regressions.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 7e84a64dd02794a59586ba58ef0864118534d3c6 |
|
10-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Fix sampling from integer textures.
On original gen4, the surface format didn't determine the return data
type from sampling like it does on g45 and later.
Fixes GL_EXT_texture_integer/texture_integer_glsl130
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 53798f90e818e9bf213c3ae4298751362a5ecd50 |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename pixel_scoreboard_clear to last_render_target for clarity.
Finding this bit in the documentation proved challenging. It wasn't in
the SEND instruction's message descriptor section, nor the data port
message descriptor section. It turns out to be part of the Render
Target Write message's control bits, and in the documentation is named
"Last Render Target Select".
Shaders that use Multiple Render Targets should set this bit on the last
RT write, but not on any prior ones.
The GPU does update the Pixel Scoreboard appropriately, but doesn't
document this bit as directly causing a scoreboard clear.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 43ccd3200c394dd4d89ed96f039ca7d6cfff972f |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove EOT parameter from brw_SAMPLE and brw_set_sampler_message.
The existing code asserted that eot == 0, as it doesn't make sense for
a thread to sample a texture as the last thing it does.
It doesn't make much sense to pass around a dead parameter either.
Especially for a function which already has a long parameter list.
So, remove the parameter and just set EOT to 0.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| d06cc42c3c85382600176d118d8bf492b4de6a55 |
|
07-Oct-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Fix computation of abs(-x) in FS
When updating a register reference to reflect the fact that we were
taking its absolute value, the fragment shader back-end failed to
clear the negate flag, resulting in abs(-x) getting computed as
-abs(x).
I also found (and fixed) a similar problem in brw_eu.h, but I'm not
aware of an actual manifestation of that problem.
Fixes piglit test glsl-fs-abs-neg-with-intermediate.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 3f5e938a9ded42ae8dc9ae2486e8d5c8b64cfe07 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Replace incorrect use of GLboolean with enum brw_compression.
brw_set_compression_control took a GLboolean as an argument, then
promptly used a switch statement to compare it with various enumeration
values. Clearly it's not actually a boolean.
Introduce a new enumeration type, enum brw_compression, and use that.
Found by converting GLboolean to bool; clang then gave warnings about
switching on a boolean and ultimately duplicated case errors.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 483f5b348b0f3c0ca7082fd2047c354e8af285e7 |
|
22-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for pull constant loads for uniform arrays.
v2: reworked the instruction emit and made use of gen6_resolve_implied_move,
from Ken's review
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 0f22f98ccd69bb5e8df3c78203bce9bc630965c1 |
|
07-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965: Make some EU emit code for DP read/write messages non-static.
We keep building these strange interfaces for DP read/write where
there's a helper function with some partially-specific,
partially-general controls, which is used in exactly one place in code
generation. Making these public will let us set up those instructions
in the one place they're to be generated.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| af3c9803d818fd33139f1247a387d64b967b8992 |
|
02-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Start adding the VS visitor and codegen.
The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's
currently controlled by the INTEL_NEW_VS=1 environment variable, and
only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 5936d96d33e767aa99f6afa92f2a6582ff04df23 |
|
16-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move IF stack handling into the EU abstraction layer/brw_compile.
This hides the IF stack and back-patching of IF/ELSE instructions from
each of the code generators, greatly simplifying the interface.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 774fb90db3e83d5e7326b7a72e05ce805c306b24 |
|
16-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Get a ralloc context into brw_compile.
This would be so much easier if we were using C++; we could simply use
constructors and destructors. Instead, we have to update all the
callers.
While we're at it, ralloc various brw_wm_compile fields rather than
explicitly calloc/free'ing them.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 1309d2ea723613f1e755dd7785d22456dd39bb08 |
|
11-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Pass brw_compile pointer to brw_set_src[01].
This makes it symmetric with brw_set_dest, which is convenient, and will
also allow for assertions to be made based off of intel->gen.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 148a32e622c5b95a4dbd9a8776fddf85ef484147 |
|
29-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add support for math instructions in 16-wide mode.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 7c647a2fe98a645723fa5eace7f7f6c5c26f4f8e |
|
14-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move the destination reg setup for 8/16 wide to the emit code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 4847f802c28e595130bda14055cd52c9b1f51cd7 |
|
09-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Constant-fold immediates in src0 of SEL instructions.
This is like what we do for add/mul, but we have to invert the
predicate to choose the other source instead.
This removes 5 extra moves of constants in nexuiz shaders. No
statistically significant performance difference on my Sandybridge
laptop (n=5).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 811c147220d2630b769e505ce4d40ef9108fe034 |
|
09-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Constant-fold immediates in src0 of CMP instructions.
This is like what we do with add/mul, but we also have to flip the
conditional test.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 2279156fe7ac9718533b8b0de90ae96100486680 |
|
16-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename brw_(IF|CONT)_gen6 functions to gen6_(IF|CONT).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 4374703a9b2ce0be105ee544c8402a932e3e1f52 |
|
22-Dec-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: explicit tell header present for fb write on sandybridge
Determine header present for fb write by msg length is not right
for SIMD16 dispatch, and if there're more output attributes, header
present is not easy to tell from msg length. This explicitly adds
new param for fb write to say header present or not.
Fixes many cases' hang and failure in GL conformance test.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 245662f3083795e272fe9ef5d4cbeb6d048cf0e5 |
|
03-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for the instruction compression bits on gen6.
Since the 8-wide first-quarter and 16-wide first-half have the same
bit encoding, we now need to track "do you want instruction
compression" in the compile state.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 843a6a308e05bd4bf2056e08ec65ac4770097b93 |
|
01-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gen6 CONTINUE instruction emit.
At this point, piglit tests for fragment shader loops are working.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 00e5a743e2ee3981a34b95067a97fa73c0f5d779 |
|
01-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gen6 BREAK ISA emit.
There are now two targets: the hop-to-end-of-block target, and the
target for where to resume execution for active channels.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 3789d5025a3200c40a39119c94c3d38a13e4b65a |
|
25-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add EU code for dword scattered reads (constant buffer array indexing).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 07cd8f46acc34b04308f81de2faf05ba33da264b |
|
22-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for pull constants to the new FS backend.
Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 99b2c8570ea6f46c6564681631f0e0750a0641cc |
|
19-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for register spilling.
It can be tested with if (0) replaced with if (1) to force spilling for all
virtual GRFs. Some simple tests work, but large texturing tests fail.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| d0c87b90a85af0bd9ca7f8cec411a458742190cc |
|
19-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add EU emit support for gen6's new IF instruction with comparison.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| f157812bbbcf9caac1f84988e738fc9d1e051056 |
|
14-Oct-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add support for ir_unop_round_even via the RNDE instruction.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 897f6d3c7d06316b0535971cc2de318157c23692 |
|
14-Oct-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Correctly emit the RNDZ instruction.
Simply using RNDU, RNDZ, or RNDE does not produce the desired result.
Rather, the RND* instructions place a value in the destination register
that may be 1 less than the correct answer. They can also set per-channel
"increment bits" in a flag register, which, if set, mean dest needs to
be incremented by 1. A second instruction - a predicated add -
completes the job.
Notably, RNDD always produces the correct answer in a single
instruction.
Fixes piglit test glsl-fs-trunc.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| fe2d4a5ea02df38c9940a726aa04bcf550fab1da |
|
22-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for POW in gen6 FS.
Fixes glsl-algebraic-pow-2 in brw_wm_glsl.c mode.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 352dff62f8005add9e71e6b5ba3b3321cb953d73 |
|
29-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Make brw_CONT and brw_BREAK take the pop count.
We always need to set it, so pass it in.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| e6ec500e19f455237828f4f3955f888ad0b56382 |
|
21-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Also use the SIMD8 FB writes for SIMD8 mode on non-SNB.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 93ba0055c325007656c14ba38302e21be3dc599f |
|
20-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Add AccWrCtl support on Sandybridge.
Whenever the accumulator results are needed, this bit must be set.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| bad29dc6dad7ed1bff46c67e61dab01f8d82b557 |
|
19-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't set the swizzle on an immediate value in the VS.
Fixes glsl-vs-if-nested (70.0 is not <= 70.000648 thanks to the
swizzle bits getting set). Some safety checks are added to make sure
this doesn't happen again as we increase the usage of immediate values
in program generation.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 2621100458e337e34166b4b769be0536f6acb32a |
|
26-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix reversed naming of the operations in compute-to-mrf optimization.
Also fix up comments, so that the difference between the two passes is
clarified.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 22f839292f48a47601e1b97a7f4679018c42d0ed |
|
26-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Move the GRF-to-MRF optimizations to brw_optimize.c.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 21eaa62ba461854003e5f74e6fc32e559e9c8455 |
|
22-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Clean up brw_dp_READ_4_vs() now that it has fewer options to support.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 96b11f1e3ee12f06be1d33bf085bf1353f23e667 |
|
22-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Support relative addressed VS constant reads using the appropriate msg.
The previous support was overly complicated by trying to use the same
1-OWORD message for both offsets.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 20be3ff57670529a410b30a1008a71e768d08428 |
|
25-Jun-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Add 'wait' instruction support
When EU executes 'wait' instruction, it stalls and sets notification
register state. Host can issue MMIO write to clear notification
register state to allow EU continue on executing again.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| ec2b92f98c2e7f161521b447cc1d9a36bce3707c |
|
11-Jun-2010 |
Brian Paul <brianp@vmware.com> |
mesa: rename src/mesa/shader/ to src/mesa/program/
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 81951393e1e675d6ca3ea052875def70d5e7ab93 |
|
14-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove constant or ignored-by-hw args from FF sync message setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 512d8ca2f34bcaa96e18daace4ae9f95e679471e |
|
11-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up VS DP4 sequences to avoid dependency control.
This is recommended by the B-Spec. I wasn't able to measure any
difference in ETQW.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 56ff30a9f97a1a7094432333906544d6138d6bf2 |
|
10-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use the PLN instruction when possible in interpolation.
Saves an instruction in PINTERP, LINTERP, and PIXEL_W from
brw_wm_glsl.c For non-GLSL it isn't used yet because the deltas have
to be laid out differently.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 8baee3d25beb616f6d5ba575684e889d60e38740 |
|
07-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Use Compr4 instruction compression mode on G4X and newer.
No statistically significant performance difference at n=3 with either
openarena or my GL demo, but cutting program size seems like a good
thing to be doing for the hypothetical app that has a working set near
icache size.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 76a5a5dace715aa629ee98a37acb3075a7de153c |
|
01-Jul-2009 |
Brian Paul <brianp@vmware.com> |
i965: use BRW_MAX_GRF, BRW_MAX_MRF
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 4fdc6ad41b843109febbe9596dde87f676a8b0e9 |
|
26-Jun-2009 |
Roland Scheidegger <sroland@vmware.com> |
i965: fix fetching constants from constant buffer in glsl path
the driver used to overwrite grf0 then use implicit move by send instruction
to move contents of grf0 to mrf1. However, we must not overwrite grf0 since
it's still used later for fb write.
Instead, do the move directly do mrf1 (we could use implicit move from another
grf reg to mrf1 but since we need a mov to encode the data anyway it doesn't
seem to make sense).
I think the dp_READ/WRITE_16 functions may suffer from the same issue.
While here also remove unnecessary msg_reg_nr parameter from the dataport
functions since always message register 1 is used.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 5590798f6d338e93ae6bee82ba5224568237ec18 |
|
12-May-2009 |
Brian Paul <brianp@vmware.com> |
i965: increase BRW_EU_MAX_INSN
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 0bc214a834bbb12b9338837dd9fca9bc389b4bc2 |
|
18-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i915: fix broken indirect constant buffer reads
The READ message's msg_control value can be 0 or 1 to indicate that the
Oword should be read into the lower or upper half of the target register.
It seems that the other half of the register gets clobbered though. So
we read into two dest registers then use a MOV to combine the upper/lower
halves.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| ee32e9b4753eca62e360f96ce61ef7ff683e6bb7 |
|
16-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: implement relative addressing for VS constant buffer reads
A scatter-read should be possible, but we're just using two READs for
the time being.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 92cc9970039d9c9385dc472fbfac58b93799f5ae |
|
15-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix VS constant buffer reads
This mostly came down to finding the right MRF incantation in the
brw_dp_READ_4_vs() function.
Note: this feature is still disabled (but getting close to done).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| cafea7528052624c8d3e4cd1c5b26a61bf04d1d0 |
|
14-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: checkpoint commit: VS constant buffers
Hook up a constant buffer, binding table, etc for the VS unit.
This will allow using large constant buffers with vertex shaders.
The new code is disabled at this time (use_const_buffer=FALSE).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 21982a2cd597aeb22d7ee2bd3a5067c58f97ca6f |
|
02-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: added brw_same_reg()
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 8127e49b93820d1768e2d298bbe238dd55c20732 |
|
31-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: added new brw_dp_READ_4() function
Used to read float[4] vectors from the constant buffer/surface.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 7d6478cfccf03c87f2b9daa541ae486dc24bb388 |
|
13-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: more register number assertions
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 2eacc4aafaa1a00135255f6025e82102dd4adbaa |
|
06-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: bump up BRW_EU_MAX_INSN
This is the size of the intermediate instruction buffer.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| c51c822ee02cb47ddba46da668577d51b7c02831 |
|
14-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: rewrite the code for handling shader subroutine calls
Previously, the prog_instruction::Data field was used to map original Mesa
instructions to brw instructions in order to resolve subroutine calls. This
was a rather tangled mess. Plus it's an obstacle to implementing dynamic
allocation/growing of the instruction buffer (it's still a fixed size).
Mesa's GLSL compiler emits a label for each subroutine and CAL instruction.
Now we use those labels to patch the subroutine calls after code generation
has been done. We just keep a list of all CAL instructions that needs patching
and a list of all subroutine labels. It's a simple matter to resolve them.
This also consolidates some redundant post-emit code between brw_vs_emit.c and
brw_wm_glsl.c and removes some loops that cleared the prog_instruction::Data
fields at the end.
Plus, a bunch of new comments.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 0d797365deb579cfeb2a32f21692515eb6904921 |
|
05-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: implement OPCODE_TRUNC (round toward zero) on vertex path.
Also, fix some RNDD vs. RNDZ confusion elsewhere.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 3b891a502b030f2ce8cd7a1aba93df11595f5c95 |
|
01-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: comments, clean-ups, re-order some functions
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 0060d4154999777bd3b17013c457ca073aa660dc |
|
06-Nov-2008 |
Gary Wong <gtw@gnu.org> |
i965: Implement missing OPCODE_NOISE3 instruction in fragment shaders.
OPCODE_NOISE4 coming later.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 58dc8b7db5829188dbb45c020ab44732d6053888 |
|
30-Oct-2008 |
Gary Wong <gtw@gnu.org> |
i965: support destination horiz strides in align1 access mode.
This is required for scatter writes in destination regions to work.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| cc96d5492038cb79806031e513365e08647d6bfa |
|
21-Jun-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
replace __inline and __inline__ with INLINE macro
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| ca73488f48e3ee278f0185bb7dcc03d7bdedb62d |
|
26-Apr-2008 |
Keith Packard <keithp@keithp.com> |
[i965] short immediate values must be replicated to both halves of the dword
The 32-bit immediate value in the i965 instruction word must contain two
copies of any 16-bit constants. brw_imm_uw and brw_imm_w just needed to
copy the value into both halves of the immediate value instruction field.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 8e444fb9e2685e3eac42beb848b08e91dc20c88a |
|
29-Jan-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: new integrated graphics chipset support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| d0ebdca4fa70506107a318e6cfd03f0fb4297897 |
|
29-Dec-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
fix fd.o bug #13847
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 3d6c4109902b555a3f8076170d572c7caeb6cbfe |
|
30-Sep-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
fragment shader function call fix, gl_FragCoord fix
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| b0b48798c7e854d2e36e0317bf94b7385e815242 |
|
29-Sep-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
support continue, fix conditional
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| d19d0596daf004b56d80f78fa1a329b43c2ebf94 |
|
21-Jun-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
support branch and loop in pixel shader
most of the sample working with some small modification
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 35707dbe57873adb5a8088cd47c13bd216e143e4 |
|
12-Apr-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Initial 965 GLSL support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 064ae479a770bf434958d673baf6f7530f642697 |
|
23-Feb-2007 |
Brian <brian@yutani.localnet.net> |
Update DRI drivers for new glsl compiler.
Mostly:
- update #includes
- update STATE_* token code
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 1b9f78195f62959601d440475a6cbba5e8046813 |
|
18-Oct-2006 |
Eric Anholt <eric@anholt.net> |
i965: Avoid branch instructions while in single program flow mode.
There is an errata for Broadwater that threads don't have the instruction/loop
mask stacks initialized on thread spawn. In single program flow mode, those
stacks are not writable, so we can't initialize them. However, they do get
read during ELSE and ENDIF instructions. So, instead, replace branch
instructions in single program flow mode with predicated jumps (ADD to the ip
register), avoiding use of the more complicated branch instructions that may
fail. This is also a minor optimization as no ENDIF equivalent is necessary.
Signed-off-by: Keith Packard <keithp@neko.keithp.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_eu.h
|