| 6886da783ac2fc549b4ffc1f42a47985044757f0 |
|
31-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Don't use brw->fragment_program in calculate_urb_setup().
Reading brw->fragment_program is nonsensical in compiler code: it
contains the currently active program (if any), not the one currently
being compiled. Attempting to access it may either lead to crashes
(null pointer dereference if no program is active) or wrong results.
Fixes piglit regressions since 9ef710575b914ddfc8e9a162d98ad554c1c217f7
on pre-Sandybridge hardware. The actual bug was created in commit
7b1fbc688999fd568e65211d79d7678562061594.
NOTE: This is a candidate for the 8.0 branch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54183
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
(cherry picked from commit 4d9abd96cc177cade79b64544096eb45bf8313a2)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 85b24b07512c5f3f05c5a3eb9561598ace97526c |
|
26-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Assume shadow sampler swizzling is <X, X, X, 1>.
Our previous assumption, SWIZZLE_XYZW, was completely bogus for depth
textures. There are no Y, Z, or W components.
DEPTH_TEXTURE_MODE has three options:
- GL_LUMINANCE: <X, X, X, 1>
- GL_INTENSITY: <X, X, X, X>
- GL_ALPHA: <0, 0, 0, X>
The default value is GL_LUMINANCE, and most applications don't seem to
alter DEPTH_TEXTURE_MODE. Make that our precompile guess.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| f3d0daf7ea7e42ff9ce11e8bd6fba1059a2406e8 |
|
26-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Index sampler program key data by linker-assigned index.
Now that most things are based on the linker-assigned index, it makes
sense to convert the arrays in the VS/WM program key as well. It seems
silly to leave them indexed by texture unit.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| ab17762c70852ca8fc400d7b5c6696d412ff2afe |
|
14-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Only set proj_attrib_mask for fixed function.
brw_wm_prog_key's proj_attrib_mask field is designed to enable an
optimization for fixed-function programs, letting us avoid projecting
attributes where the divisor is 1.0.
However, for shaders, this is not useful, and is pretty much impossible
to guess when building the FS precompile key. Turning it off for
shaders should allow the precompile to work and not lose much.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Suggested-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| b6b1fc1261e86e2aa03ae8d2dd587c88a207354f |
|
14-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't set vp_outputs_written in the WM program key on Gen6+.
It's only used by on pre-Sandybridge hardware.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a3685544e1e88828c4931059686cf3acc199079c |
|
14-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't set iz_lookup the FS precompile's program key on Gen6+.
We already changed the actual program key builder to only set these bits
on gen < 6; this patch just brings the precompile state back in line so
it doesn't mismatch every time.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 43e3a7533d5537e48cef23588131dd25d938ee4b |
|
14-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Fix the scaling of seconds to ms in perf debug.
*headdesk*
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 006c1a3c652803e2ff8d5f7ea55c9cb5d8353279 |
|
07-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add perf debug for stalls during shader compiles.
v2: fix bad comment from before I gave up and decided to just use doubles.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| fc3b7c9b56701f23b002543de33a8d8c43f9bdc2 |
|
12-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add performance debug for shader recompiles.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| d72ff03e699e78381049e29d89163519e6730dd4 |
|
12-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add INTEL_DEBUG=perf for failure to compile 16-wide shaders.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 7426d9d7699452f15f3288e781e1791d8d00a64a |
|
19-Jul-2012 |
Olivier Galibert <galibert@pobox.com> |
i965/fs: Fix the FS inputs setup when some SF outputs aren't used in the FS.
If there was an edge flag or a two-side-color pair present, we'd end up
mismatched and read values from earlier in the VUE for later FS inputs.
v2: Fix regression in gles2conform shaders generating point size. (change by
anholt)
Signed-off-by: Olivier Galibert <galibert@pobox.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 90de96ff0d6d54ba0f9a337a6a107acf4134682d |
|
21-Jun-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add support for loading uniform buffer variables as pull constants.
Variable array indexing isn't finished, because the lowering pass
turns it all into conditional moves of constant index accesses so I
can't test it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 454dc83f66643e66ea7ee9117368211f0cfe84d7 |
|
21-Jun-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Communicate the pull constant block read parameters through fs_regs.
I wanted to add the surface index as a variable value for UBO support,
and a reg seemed like the obvious way to go. This exposes more of the
information to CSE, which we'll probably want to apply to pull
constant loads for UBOs eventually (you might access 4 floats in a
row, each of which would produce an oword block read of the same
block).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| cc44aa77490e1360b099eb0b887266f434298b4f |
|
21-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965: Remove unused param conversion code.
Ever since ctx->NativeIntegers was set, the conversion flag has been
PARAM_NO_CONVERT.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| d08fdacd58dfa6b1926e9df4707dd9e8dd5370c5 |
|
20-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Avoid unnecessary recompiles for shaders that don't use dFdy().
The i965 back-end needs to compile dFdy() differently for FBOs and
window system framebuffers, because Y coordinates are flipped between
the two (see commit 82d2596: i965: Compute dFdy() correctly for FBOs).
This patch avoids unnecessarily recompiling shaders that don't use
dFdy(), by only setting render_to_fbo in the wm program key if the
shader actually uses dFdy().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a454f8ec6df9334df42249be910cc2d57d913bff |
|
07-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs.h: Refactor tests for instructions modifying a register.
There's one instance of a potential behavior change: propagate_constants may
now propagate into a part of a vgrf after a different part of it was
overwritten by a send that returns multiple registers. I don't think we ever
generate IR that meets that condition, but it's something to note if we bisect
behavior change to this.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| fc01376c50c15938f3b78431023ca3281304663d |
|
06-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Replace usage is_tex() with regs_written() checks.
In these places, we care about any sort of send that hits more than one reg,
not just textures. We don't yet have anything else returning more than one
reg, so there's no change.
v2: Use mlen instead of is_tex() for the is-it-a-send check.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a6411520b40d59a8806289c7aaea4a6b26a54443 |
|
06-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Rename virtual_grf_next to virtual_grf_count.
"count" is a more useful name, since most of the time we're using it for
looping over the variables.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| b546aebae922214dced54c75e6f64830aabd5d1c |
|
10-Jul-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Delete previous workaround for textureGrad with shadow samplers.
It had many problems:
- The shadow comparison was done post-filtering.
- It required state-dependent recompiles whenever the comparison
function changed.
- It didn't even work: many cases hit assertion failures.
- I never implemented it for the VS.
The new lowering pass which converts textureGrad to textureLod by
computing the LOD value works much better.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 2343fe9a5d1786413453e6e8e5c7700143d68a26 |
|
05-Jun-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Invalidate live intervals in passes that remove an instruction.
Since live intervals are based on ip, removing an instruction trashes
the intervals unless we were to go do some surgery. These happen to
usually remove a use of a grf, so it's time to recalculate, anyway.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
NOTE: This is a candidate for the 8.0 release branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| fe27916ddf41b9fb60c334c47c1aa81b8dd9005e |
|
04-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Move class functions from the header to .cpp files.
Cuts compile time for brw_fs.h changes from 2.7s to .7s and reduces
i965_dri.so size by 70k.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 8313f44409ceb733e9f8835926364164237b3111 |
|
21-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Fix centroid interpolation of unlit pixels.
From the Ivy Bridge PRM, Vol 2 Part 1 p280-281 (3DSTATE_WM:
Barycentric Interpolation Mode):
"Errata: When Centroid Barycentric mode is required, HW may
produce incorrect interpolation results when a 2X2 pixels have
unlit pixels."
To work around this problem, after doing centroid interpolation, we
replace the centroid-interpolated values for unlit pixels with
non-centroid-interpolated values (which are interpolated at pixel
centers). This produces correct rendering at the expense of a slight
increase in shader execution time.
I've conditioned the workaround with a runtime flag
(brw->needs_unlit_centroid_workaround) in the hopes that we won't need
it in future chip generations.
Fixes piglit tests "EXT_framebuffer_multisample/interpolation {2,4}
{centroid-deriv,centroid-deriv-disabled}". All MSAA interpolation
tests pass now.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| d1056541e239dfcee0ad6af2fd2d9fab37dbf025 |
|
18-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Add backend support for centroid interpolation.
This patch causes the fragment shader to be configured correctly (and
the correct code to be generated) for centroid interpolation. This
required two changes: brw_compute_barycentric_interp_modes() needs to
determine when centroid barycentric coordinates need to be included in
the pixel shader thread payload, and
fs_visitor::emit_general_interpolation() needs to interpolate using
the correct set of barycentric coordinates.
Fixes piglit tests "EXT_framebuffer_multisample/interpolation {2,4}
centroid-edges" on i965.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| cf0e7aa9f8bc9c175ebd9b2ab3a8bfec4afc5abf |
|
21-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/fs: Refactor interpolation code to prepare for adding centroid support.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 82d25963a838cfebdeb9b080169979329ee850ea |
|
20-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Compute dFdy() correctly for FBOs.
On i965, dFdx() and dFdy() are computed by taking advantage of the
fact that each consecutive set of 4 pixels dispatched to the fragment
shader always constitutes a contiguous 2x2 block of pixels in a fixed
arrangement known as a "sub-span". So we calculate dFdx() by taking
the difference between the values computed for the left and right
halves of the sub-span, and we calculate dFdy() by taking the
difference between the values computed for the top and bottom halves
of the sub-span.
However, there's a subtlety when FBOs are in use: since FBOs use a
coordinate system where the origin is at the upper left, and window
system framebuffers use a coordinate system where the origin is at the
lower left, the computation of dFdy() needs to be negated for FBOs.
This patch modifies the fragment shader back-ends to negate the value
of dFdy() when an FBO is in use. It also modifies the code that
populates the program key (brw_wm_populate_key() and
brw_fs_precompile()) so that they always record in the program key
whether we are rendering to an FBO or to a window system framebuffer;
this ensures that the fragment shader will get recompiled when
switching between FBO and non-FBO use.
This will result in unnecessary recompiles of fragment shaders that
don't use dFdy(). To fix that, we will need to adapt the GLSL and
NV_fragment_program front-ends to record whether or not a given shader
uses dFdy(). I plan to implement this in a future patch series; I've
left FIXME comments in the code as a reminder.
Fixes Piglit test "fbo-deriv".
NOTE: This is a candidate for stable release branches.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| f220f73b9c5aca16ca21ea8bbbbf8718703b12cf |
|
08-May-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Do more register coalescing by using the interference graph.
By using the live variables code for determining interference, we can
handle coalescing in the presence of control flow, which the other
register coalescing path couldn't.
Total instructions: 207184 -> 206990
74/1246 programs affected (5.9%)
33993 -> 33799 instructions in affected programs (0.6% reduction)
There is a newerth shader that loses out, because of some extra MOVs
that now get their dead-code nature obscured by coalescing. This
should be fixed by doing better at dead code elimination.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| d7787adda8006506545256547d8d590a282487af |
|
08-May-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add support for copy propagation.
We could do more by handling abs/negate and non-GRF sources, but this is
a good start. Improves tropics performance 0.30% +/- .17% (n=43).
shader-db results:
Total instructions: 208032 -> 207184
60/1246 programs affected (4.8%)
23286 -> 22438 instructions in affected programs (3.6% reduction)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a4e9b5a768d2d9e59b6054148afb6a6b94c0e4e6 |
|
11-May-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Add a local common subexpression elimination pass.
Total instructions: 18210 -> 17836
49/163 programs affected (30.1%)
12888 -> 12514 instructions in affected programs (2.9% reduction)
This reduces Lightsmark's "Scale down filter" shader from 395
instructions to 283, a whopping 28%. It also reduces register pressure
significantly: the SIMD8 program now uses 29 registers instead of 101,
giving us more than enough room for a SIMD16 program.
v2: Add && !inst->conditional_mod to the "skip some instructions" check.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| d1029f99884e2ba7f663765274cd6bdb4f82feed |
|
11-May-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Use a const reference in fs_reg::equals instead of a pointer.
This lets you omit some ampersands and is more idiomatic C++. Using
const also marks the function as not altering either register (which
was obvious, but nice to enforce).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4433b0302d0aa9dc61002e8bb4fd1b752b0be338 |
|
20-Apr-2012 |
Brian Paul <brianp@vmware.com> |
intel: use _mesa_is_winsys/user_fbo() helpers
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 34b17ee598e855e1090a455c2dac31ed8104954b |
|
11-Apr-2012 |
Eric Anholt <eric@anholt.net> |
i965: Move the old live interval analysis code next to the new live vars code.
I'm about to replace the insides of this using the new analysis.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 32ae8d3b321185a85b73ff703d8fc26bd5f48fa7 |
|
10-Mar-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Try to avoid generating extra MOVs to do saturates.
This change (before the previous two) produced a .23% +/- .11%
performance improvement in Unigine Tropics at 1024x768 on IVB.
Total instructions: 269270 -> 262649
614/2148 programs affected (28.6%)
179386 -> 172765 instructions in affected programs (3.7% reduction)
v2: Move some of the logic of finding the instruction that produced
the result of an expression tree to a helper.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 43af02ac731dac7d80f7e47feb0c80e4da156769 |
|
27-Feb-2012 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
i965: handle gl_PointCoord for Gen4 and Gen5 platforms
This patch add the support of gl_PointCoord gl builtin variable for
platform gen4 and gen5(ILK).
Unlike gen6+, we don't have a hardware support of gl_PointCoord, means
hardware will not calculate the interpolation coefficient for you.
Instead, you should handle it yourself in sf shader stage.
But badly, gl_PointCoord is a FS instead of VS builtin variable, thus
it's not included in c.vue_map generated in VS stage. Thus the current
code doesn't aware of this attribute. And to handle it correctly, we
need add it to c.vue_map manually to let SF shader generate the needed
interpolation coefficient for FS shader. SF stage has it's own copy of
vue_map, thus I think it's safe to do it manually.
Since handling gl_PointCoord for gen4 and gen5 platforms is somehow a
little special, I added a lot of comments and hope I didn't overdo it ;)
v2: add a /* _NEW_BUFFERS */ comment to note the state flag dependency
and also add the _NEW_BUFFERS dirty mask (Eric).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45975
Piglit: glsl-fs-pointcoord and fbo-gl_pointcoord
NOTE: This is a candidate for stable release branches.
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a7f46eadea4555ed377928d4e3f89db4a445312e |
|
09-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Report the failure message when failing to compile the fragment shader.
We just abort later, but at least this should result in more
informative bug reports.
NOTE: This is a candidate for release branches.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a4586d2e2e444d1212d4abfd1ea5bbeff4503feb |
|
27-Jan-2012 |
Eric Anholt <eric@anholt.net> |
intel: Comment typo fix.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 30f86aec01e1e1df4265d10a4618e34e9b8fec95 |
|
06-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Fix projector==1.0 optimization pre-gen6.
The optimization was supposed to turn an attribute component that was
always 1.0 into a mov of 1.0. But by leaving loop this patch removes
out of that test, we applied the projection correction to the 1.0 and
got some other value, breaking openarena once it was converted to
using the new compiler backend.
Originally this hunk was separate from the former loop to make the
generated instructions slightly better pipelined. We now have
automatic instruction scheduling to handle that, and the generated
instruction sequence looked the same to me after this change (except
for the bugfix).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 069901e2f5a8f4a58047d25335f2526f1acc7234 |
|
19-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Allow constant propagation into IF with embedded compare.
This saves a couple of instructions on most programs with control
flow. More interestingly, 6 shaders from unigine sanctuary now fit
into 16-wide without register spilling.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 1b05fc7cdd0e5d77b50bc8ee2f2c851da5884d72 |
|
07-Dec-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Factor out texturing related data from brw_wm_prog_key.
The idea is to reuse this for the VS and (in the future) GS as well.
v2: Include yuvtex data since we're not dropping GL_MESA_ycbycr.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| febad1779ae5cb5c85d66c2635baea62da52d2fa |
|
26-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB.
We'll be reusing most of these for the VS shortly. The one exception is
TXB (texturing with LOD bias), which is explicitly forbidden in the VS.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a73c65c5342bf41fa0dfefe7daa9197ce6a11db4 |
|
18-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Enable faster workaround-free math on Ivybridge.
According to the documentation, Ivybridge's math instruction works in
SIMD16 mode for the fragment shader, and no longer forbids align16 mode
for the vertex shader.
The documentation claims that SIMD16 mode isn't supported for INT DIV,
but empirical evidence shows that it works fine. Presumably the note
is trying to warn us that the variant that returns both quotient and
remainder in (dst, dst + 1) doesn't work in SIMD16 mode since dst + 1
would be sechalf(dst), trashing half your results. Since we don't use
that variant, we don't care and can just enable SIMD16 everywhere.
The documentation also still claims that source modifiers and
conditional modifiers aren't supported, but empirical evidence and
study of the simulator both show that they work just fine.
Goodbye workarounds. Math just works now.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 8fad0f99989866eeb72889a84f12f6f817334ddb |
|
02-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Fix constant propagation into 32-bit integer MUL.
i965's MUL instruction can't take an immediate value as its first
argument. So normally, if constant propagation wants to propagate a
constant into the first argument of a MUL instruction, it swaps the
order of the two arguments.
This doesn't work for 32-bit integer (and unsigned integer)
multiplies, because the MUL operation is asymmetric in that case (it
multiplies 16 bits of one operand by 32 bits of the other).
Fixes piglit tests {vs,fs}-multiply-const-{ivec4,uvec4}.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 9734bd05608c00a1d84851f3d46d5deb52e75d5e |
|
25-Oct-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Fix flat integral varyings.
Previously, the vertex and fragment shader back-ends assumed that all
varyings were floats. In GLSL 1.30 this is no longer true--they can
also be of integral types provided that they have an interpolation
qualifier of "flat".
This required two changes in each back-end: assigning the correct type
to the register that holds the varying value during shader execution,
and assigning the correct type to the register that ties the varying
value to the rest of the graphics pipeline (the message register in
the case of VS, and the payload register in the case of FS).
Fixes piglit tests fs-int-interpolation and fs-uint-interpolation.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 5aa96286e7e1a5380673eb75e8653616b48751fd |
|
22-Oct-2011 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6+: Add support for noperspective interpolation.
This required the following changes:
- WM setup now makes the appropriate set of barycentric coordinates
(perspective vs. noperspective) available to the fragment shader,
based on whether the shader requires perspective interpolation,
noperspective interpolation, both, or neither.
- The fragment shader backend now uses the appropriate set of
barycentric coordiantes when interpolating, based on the
interpolation mode returned by
ir_variable::determine_interpolation_mode().
- SF setup now uses gl_fragment_program::InterpQualifier to determine
which attributes are to be flat shaded (as opposed to the old logic,
which only flat shaded colors).
- CLIP setup now ensures that the clipper outputs non-perspective
barycentric coordinates when they are needed by the fragment shader.
Fixes the remaining piglit tests of interpolation qualifiers that were
failing:
- interpolation-flat-*-smooth-none
- interpolation-flat-other-flat-none
- interpolation-noperspective-*
- interpolation-smooth-gl_*Color-flat-*
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| f8386a29f07c6a41c4afb99fc3ecd9f18e9151e8 |
|
21-Oct-2011 |
Paul Berry <stereotype441@gmail.com> |
i965/fs: use determine_interpolation_mode().
This patch changes how fs_visitor::emit_general_interpolation()
decides what kind of interpolation to do. Previously, it used the
shade model to determine how to interpolate colors, and used smooth
interpolation on everything else. Now it uses
ir_variable::determine_interpolation_mode(), so that it respects GLSL
1.30 interpolation qualifiers.
Fixes piglit tests interpolation-flat-*-smooth-{distance,fixed,vertex}
and interpolation-flat-other-flat-{distance,fixed,vertex}.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| e04bdeae82797dbdcf6f544a997a4626fdfd4aee |
|
22-Oct-2011 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6+: Parameterize barycentric interpolation modes.
This patch modifies the fragment shader back-end so that instead of
using a single delta_x/delta_y register pair to store barycentric
coordinates, it uses an array of such register pairs, one for each
possible intepolation mode.
When setting up the WM, we intstruct it to only provide the
barycentric coordinates that are actually needed by the fragment
shader--that is computed by brw_compute_barycentric_interp_modes().
Currently this function returns just
BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because this is the only
interpolation mode we support. However, that will change in a later
patch.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 102bdd26e1acf1ebf75ef85b62df2400239fd480 |
|
21-Oct-2011 |
Paul Berry <stereotype441@gmail.com> |
i965/fs: Fix split_virtual_grfs() when delta_xy not in a virtual register.
This patch modifies the special case in
fs_visitor::split_virtual_grfs() that prevents splitting from being
applied to the delta_x/delta_y register pair (this register pair needs
to remain contiguous so that it can be used by the PLN instruction).
When gen>=6, this register pair is in a fixed location, not a virtual
register, so it was in no danger of being split. And
split_virtual_grfs' attempt not to split it was preventing some other
unrelated register from being split.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 73b0a28ba8b3e2ab917d4c729f34ddbde52c9e88 |
|
04-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Fix comparisions with uint negation.
The condmod instruction ends up generating garbage condition codes,
because apparently the comparison happens on the accumulator value (33
bits for UD), not the truncated value that would be written.
Fixes fs-op-neg-*
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| d06cc42c3c85382600176d118d8bf492b4de6a55 |
|
07-Oct-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Fix computation of abs(-x) in FS
When updating a register reference to reflect the fact that we were
taking its absolute value, the fragment shader back-end failed to
clear the negate flag, resulting in abs(-x) getting computed as
-abs(x).
I also found (and fixed) a similar problem in brw_eu.h, but I'm not
aware of an actual manifestation of that problem.
Fixes piglit test glsl-fs-abs-neg-with-intermediate.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| de772c402215b956ab3aa0875330fc1bf7cdf95b |
|
21-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Use gl_shader_program::_LinkedShaders instead of FragmentProgram
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4170227407eea7fd8287b17480a37309bf73f4e4 |
|
07-Oct-2011 |
Brian Paul <brianp@vmware.com> |
i965: silence unused var warnings in non-debug builds
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| b9af592dfa8f8d0fe9f29c2d48bf6846cbd5c50f |
|
29-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Reverse the operands for INT DIV prior to Gen6.
Apparently on Gen4 and 5, the denominator comes first.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| ff8f272b0d02b41a0ce34ab6af7119b9e06f4961 |
|
29-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Implement integer quotient and remainder math operations.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 30be2cc6c7c3378ee17885b5bf41d7ae53bf6fe0 |
|
26-Aug-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Implement texelFetch() on Ironlake and Sandybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 23eec54bb0f368d9c88894b544b4af8f01cae2ae |
|
07-Sep-2011 |
Brian Paul <brianp@vmware.com> |
i965: add casts to silence int/enum conversion warnings
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 51e7b058750cc480c296d45f773d7a5a662457f5 |
|
06-Sep-2011 |
Brian Paul <brianp@vmware.com> |
mesa: put _mesa_ prefix on vert_result_to_frag_attrib()
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 6489a1d5bab75589569658d374257bf23cb67a23 |
|
30-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
Refactor code that converts between gl_vert_result and gl_frag_attrib.
Previously, this conversion was duplicated in several places in the
i965 driver. This patch moves it to a common location in mtypes.h,
near the declaration of gl_vert_result and gl_frag_attrib.
I've also added comments to remind us that we may need to revisit the
conversion code when adding elements to gl_vert_result and
gl_frag_attrib.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 2f0edc60f4bd2ae5999a6afa656e3bb3f181bf0f |
|
26-Aug-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Fix Android build by removing relative includes
Replace each occurence of
#include "../glsl/*.h"
with
#include "glsl/*.h"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| ecf8963754489abfb5097c130a9bcd4cdb76b6bd |
|
19-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Implement textureSize (TXS) on Gen5+.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| e98ee06776e0ba055e0194836d5813a0bc7e7795 |
|
12-Aug-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Don't double-convert integer/boolean uniforms.
When ctx->Const.NativeIntegers is set, Core Mesa loads integer/boolean
uniforms directly, rather than loading the floating point equivalent.
So, when that's set, we don't need to perform any conversions.
Unfortunately, we can't properly support native integers with the old
vertex shader backend, so this patch leaves them disabled for now.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 7fbe7fe13359d3f349664410ec73d7bd48824ed6 |
|
11-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Run the shader backend at link time and return compile failures.
Link failure is something that shouldn't happen, but we sometimes want
it during development. The precompile also allows analysis of shader
codegen with shader-db.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 65b5cbbcf783f6c668ab5b31a0734680dd396794 |
|
05-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965: Rename math FS_OPCODE_* to SHADER_OPCODE_*.
I want to just use the same enums in the VS.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 6034b9a5124475d300d0678bd2fb6160865fa972 |
|
03-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Create a shared enum for hardware and compiler-internal opcodes.
This should make gdbing more pleasant, and it might be used in sharing
part of the codegen between the VS and FS backends.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| c9e81fe14f36933617c862efb15ae09194485eab |
|
15-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop the reg/hw_reg distinction.
"reg" was set in only one case, virtual GRFs pre register allocation,
and would be unset and have hw_reg set after allocation. Since we
never bothered with looking at virtual GRF number after allocation
anyway, just use the same storage and avoid confusion.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| b76378d46a211521582cfab56dc05031a57502a6 |
|
04-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Eliminate the magic nature of virtual GRF 0.
This was a debugging aid at one point -- virtual grf 0 should never be
allocated, and it would be used if undefined register access occurred
in codegen. However, it made the confusing register allocation code
even more confusing by indexing things off of 1 all over.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| ee0373b833155804bb8846c6f05f897b9ee5afa6 |
|
26-Jul-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Don't upload unused uniform components.
This saves both register space and upload bandwidth for unused values.
Note that previously we were relying on the visitor not initially
generating references to different sets of uniforms between the 8-wide
and 16-wide code generation, and now we're relying on them dead-code
eliminating the same stuff, too.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4683529048ee133481b2d8f1cae1685aa1736f9a |
|
04-Aug-2011 |
Bryan Cain <bryancain3@gmail.com> |
Merge branch 'glsl-to-tgsi'
Conflicts:
src/mesa/state_tracker/st_atom_pixeltransfer.c
src/mesa/state_tracker/st_program.c
|
| 54db6e618e43abbd69b59e0a03e2b6ec83d3120f |
|
30-Jun-2011 |
Bryan Cain <bryancain3@gmail.com> |
r200, r600c, i965: fix build
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| f710b8c7501f29f5f8941e757ea1066cbeb03305 |
|
23-Jul-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Allow register coalescing where the source is a uniform.
Removes 0.8% of the fragment shader instructions on Unigine Tropics.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a8b86459a1bb74cfdf0d63572a9fe194b2b5b53f |
|
23-Jul-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Optimize a * 1.0 -> a.
This appears in our instruction stream as a result of the
brw_vs_constval.c handling.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 6d8d6b41b85a18685351f3023a4cd41266ba9e68 |
|
23-Jul-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: If we see a RCP of a constant, try to constant fold it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| eb30820f268608cf451da32de69723036dddbc62 |
|
23-Jul-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Port texture projection avoidance optimization from the old backend.
This is part of fixing a ~1% performance regression in OpenArena when
changing the fixed function fragment shader to using the new backend.
Right now this just avoids the LINTERP of the projector, not the math
using it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 44ffb4ae207e48f78fae55925601b8708ed09c1d |
|
29-Jul-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Stop using the exec_list iterator.
The old style has gone out of favor in the project, but I kept copy
and pasting from existing iterator code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 6430df37736d71dd2bd6f1fe447d39f0b68cb567 |
|
10-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Add support for TXD with shadow comparisons.
Our hardware doesn't have a sample_d_c message, so we have to do a
regular sample_d and emit instructions to manually perform the
comparison.
This requires a state dependent recompile whenever the sampler's compare
mode or function change. This adds the per-sampler comparison functions
to brw_wm_prog_key, but only sets them when the sampler's compare mode
is GL_COMPARE_R_TO_TEXTURE (i.e. only for shadow sampling).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| ad9481e12813d5f1dec95ce123927e132fa935fb |
|
11-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Check for compilation failure and bail before optimizing.
Prior to this patch, it would attempt to optimize and allocate registers
for the program even if it failed to compile. This seems wasteful.
More importantly, the "message length > 11" failure seems to choke the
instruction scheduler, making it somehow use an undefined value and
segmentation fault.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| c173541d9769d41a85cc899bc49699a3587df4bf |
|
27-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use state streaming on programs, and state base address on gen5+.
There will be a little bit of thrashing of the program cache BO as the
cache warms up, but once the application is in steady state, this
reduces relocations on gen5 and later.
On my T420 laptop, cairogl firefox-talos-gfx performance improves 2.6%
+/- 1.3% (n=6). No statistically significant performance difference
on nexuiz (n=5).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 23ef4a6063668c187d00a0502207f0c03be5f994 |
|
10-Jun-2011 |
Eugeni Dodonov <eugeni@mandriva.com> |
Fix format not a string literal error with -Werror=format-security
A trivial fix for error: format not a string literal and no format
arguments with compiling with -Werror=format-security flags.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| c331b3123ecda127919458e24848b7c1596525ac |
|
12-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Use the embedded compare in SEL on gen6+.
This avoids the extra CMP and the predication on SEL, so in addition
to one less instruction, it makes scheduling less constrained.
Improves glbenchmark Egypt performance 0.6% +/- 0.2% (n=3). Reduces
FS instruction count across affected shaders in shader-db by 1.3%
without regressing any.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 8752764076e5b3f052a57e0134424a37bf2e9164 |
|
17-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Do a FS compile up front at link time to produce link errors.
At glLinkShaders time, a fail() call in FS compile in 8-wide (the one
that's required to succeed, though we may relax that at some point for
pre-Ironlake performance) will now report out as a link error.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| d1f70a8a6c6ec7007bad22d3d6013415be2d243a |
|
25-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Split the GLSL IR -> FS LIR visitor to brw_fs_visitor.cpp.
We now have:
brw_fs.cpp handles calling out to everything and optimization.
brw_fs_visitor.cpp handles translating to our LIR.
brw_fs_emit.cpp handles emitting from our LIR to native code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 11dd9e9c0fcf9985b90ff4b63b2833345fece027 |
|
25-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp
This is all separate from the visitor and the optimization passes
which feed into it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| b7b700aeb0eab2cae26a01d9db42feea969333c7 |
|
26-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move a couple of GLSL IR -> BRW helper functions to brw_shader.cpp.
These will be used by the VS backend as well.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 14b86f3c9131c1b26b01e07679cc899df0885b23 |
|
26-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move non-FS-specific shader support to brw_shader.cpp.
These only existed in brw_fs.cpp because it was the only .cpp file in
the area when I wrote them.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 53c89c67f33639afef951e178f93f4e29acc5d53 |
|
27-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Avoid generating MOVs for assignments of expressions.
No statistically significant difference measured in 3dbenchmark
egypt/pro. It does reduce fragment shader instructions across
shader-db by 0.3%.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 1791857d7d950d3d2834bbb09b495f51f43ef7c1 |
|
17-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Move the computation of register block count from unit to compile.
No net code size change, but unit update is down 0.8% code size
pre-gen6.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 615117ce4efd041459f7d4b0c77aa8e248345e66 |
|
23-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Track fixed GRF regs separate from allocated GRF file in scheduling.
There's an assumption here that fixed GRFs will never intersect with
the allocated GRFs. That's true today, though it might change some
day if we decide to register-allocate the regs containing push
constants once they're dead.
This fixes a regression in 0f7325b89038937bd428f7c89ed9859189a0ab0b in
Lightsmark from the texture instructions now containing g0 references
instead of having that be implied. Performance is improved 15.2% +/-
3.6% (n=3).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34968
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| f147599ef4b0d14c25a7e0d3f9f1c9b0229bb6fc |
|
19-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove linear_color for GL_PERSPECTIVE_CORRECTION_HINT.
From the GL 2.1 spec:
"Required perspective-correct interpolation for all fragment
attributes except depth in sections 3.4.1 and 3.5.1, effectively
making GL PERSPECTIVE CORRECT HINT a no-op."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| fa42de5ad7ebbc0b81ce6ba0553742f0413690a7 |
|
24-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix assertion failures in unused brw_reg setup by deleting it.
I was using undefined values to create an unused value. Go me.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=37366
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 9be8524af753791d26fbd65417c5380b4d934296 |
|
21-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix sampling on Ivybridge after headerless change.
Fixes a regression since 90e922267a89fa9bef254bb257405531ceff7356.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 24de02acaca2ed2e5149a6a026b8707cd0d6d27f |
|
21-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove "TXD" from justification of sampler message headers.
The coordinate offsets set in the m1 header are for textureOffset;
they have nothing to do with textureGrad (TXD).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 90e922267a89fa9bef254bb257405531ceff7356 |
|
12-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Don't emit a header on gen5+ sample messages unless required.
Improves glbenchmark egypt performance 0.6% +/- 0.4% (n=6).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4bbc7915f16a8b0dcead3f34aa1b4f0328147bea |
|
12-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Fix GPU hang on texture2d-bias on pre-Ironlake.
In the 16-wide rework, I missed that we were setting some things to be
SIMD16 mode (corresponding to their setup in emit_texture_gen4()).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| b126a0c0cb30b1e2f2df1953fe14d8596d1cf4f7 |
|
02-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for correct GL_CLAMP behavior by clamping coordinates.
This removes the stupid strict-conformance fallback code I broke when
adding ARB_sampler_objects.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36572
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 7592f005608e6c03d53c18d27d9af84bde802014 |
|
11-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Drop the viewport index/rtai clearing in gen6 fb writes.
These fields are documented to be in the payload, and though the FB
write docs say they *aren't* in the payload, for all other fields the
payload and header is structured so that no overwriting is required
except for non-default options.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 136eb2bde769713b100351ff96bceb970f068c0a |
|
10-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add support for "if" statements in 16-wide mode on gen6+.
It turns out there's nothing in the hardware preventing this. It
appears that it ought to work on pre-gen6 as well, but just produces
GPU hangs.
Improves glbenchmark Egypt framerate 4.4% +/- 0.3% (n=3), and Pro by
2.6% +/- 0.6% (n=3).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 27b03926618ddcafabb7b61e652fe6458b017b24 |
|
11-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Fix discard and alpha test in 16-wide.
As of gen6, alt-mode (which we use) MOVs of floats are not raw --
they'll modify infs/nans. This broke discard and alpha test in
16-wide, where apparently the upper 8 bits of the pixel enables being
set were causing the whole value to get trashed upon being moved.
Treating the values as UD instead of float makes sure they get
preserved. While I'm here, replace the two 8-wide moves of the halves
of the header with a single compressed move.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36648
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 51761a1aefd31b7df12edd9467ac630b9cbbbbc9 |
|
11-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Cut an instruction and a temporary from gen6 discard statements.
I thought I was thwarted initially when I couldn't do conditional mod
on a MOV, and couldn't use two immediate constants in one instruction.
But g0 != g0 is also a way to produce a failing comparison.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 5dd5be69f099211db027b6e39150cacefcfdf8b6 |
|
09-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Fix compiler warnings about dead code from 963431829055f63ec94d
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 2a95568f64a6641a49a2d4855272e9be2ac2db6d |
|
11-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Avoid register coalescing away MATH workarounds on Ivybridge.
The MATH instruction cannot handle source modifiers, even on Gen7.
So, apply this workaround for Sandybridge on Ivybridge as well.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 64ce592679a5b08d66e3cbbf964f9e695e14aee1 |
|
16-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add support for IF/ELSE/ENDIF control flow on Ivybridge.
Ivybridge's IF instruction doesn't support conditional modifiers.
It also introduces UIP, which must point to the ENDIF instruction.
ELSE and ENDIF remain the same except that JIP moves from dst to src1.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| ff6e3c73f6553cd29b915497b5b00e3ef158a27d |
|
29-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add support for Ivybridge texturing messages.
Ivybridge puts the shadow comparator first, then lod/bias, and finally
the coordinate---unlike previous generations which always reserved four
slots for the coordinate at the beginning.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 5936d96d33e767aa99f6afa92f2a6582ff04df23 |
|
16-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move IF stack handling into the EU abstraction layer/brw_compile.
This hides the IF stack and back-patching of IF/ELSE instructions from
each of the code generators, greatly simplifying the interface.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 37642518b8864ce751754957b08cdb437998f4e7 |
|
29-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add support for compute-to-mrf in 16-wide mode.
This is more painful than instruction scheduling, as we have to
compare two MRF writes to see if they coincide, and have to handle
partial GRF writes before that (for example, the result of a math
instruction written to color).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 445289b5093acb9abaf7e0a89bfa319fcb4a1c31 |
|
29-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Typo fix a comment.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 0834607a891f7c2529d1f2cdeca28b6e98899f8b |
|
25-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Enable constant propagation in 16-wide.
All that needed fixing was skipping the newly-possible
uncompressed/sechalf partial GRF constant writes.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 3b20f999bb7e9056e83ca09a842a9747d4ac1674 |
|
23-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add support for 16-wide dispatch with uniforms in use.
This is glued in in a bit of an ugly way -- we rely on the uniforms
having been set up by 8-wide dispatch, and we just reuse them without
the ability to add new uniforms for any reason, since the 8-wide
compile is already completed. Today, this all works out because our
optimization passes are effectively the same for both and even if they
weren't, we don't reduce the set of uniforms pushed after
optimization.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| b943b9b1a696cf51adfb2a18bcb9cf503fb2737f |
|
23-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add a little whitespace between shader dumping debug.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 9c57780dc0604f871650c5d23c06d627d964d803 |
|
28-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add support for compr4 MRF writes.
These reduce an emitted (not decoded) instruction per shader on
g4x/gen5, but may allow for additional register coalescing as well.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 42ad2f0b9b6a18f1613f6d915a46b4a4a89c5aa2 |
|
14-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add support for 16-wide dispatch on gen5.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 662f1b48bd1a02907bb42ecda889a3aa52a5755d |
|
12-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add initial support for 16-wide dispatch on gen6.
At this point it doesn't do uniforms, which have to be laid out the
same between 8 and 16. Other than that, it supports everything but
flow control, which was the thing that forced us to choose 8-wide for
general GLSL support.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 76b7a0c1af23838cb5100424a2a88d621b881d05 |
|
24-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add support for discard instructions in 16-wide mode.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 148a32e622c5b95a4dbd9a8776fddf85ef484147 |
|
29-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add support for math instructions in 16-wide mode.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 54990673a65b72fd222aeafc19f3a384ce597146 |
|
24-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Fix interference calculation of pixel_[xy] in 16-wide.
Fixes glsl-fs-ceil in that mode, which produced the code in the comment.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| af20328271425c217630b5114ee172bd8387a91a |
|
23-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Disable some optimization passes under 16-wide for now.
These are fixable for 16, but that can wait until after it's basically
working.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 8575d1836249309048d77d342671aad65c7fa7ff |
|
13-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add support for 16-wide texturing on gen5+.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 141b0bb2779c80d3cd3fd21d2e9d10efa0433f26 |
|
21-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add support for computing pixel_[xy] in 16-wide.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 7c647a2fe98a645723fa5eace7f7f6c5c26f4f8e |
|
14-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move the destination reg setup for 8/16 wide to the emit code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4847f802c28e595130bda14055cd52c9b1f51cd7 |
|
09-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Constant-fold immediates in src0 of SEL instructions.
This is like what we do for add/mul, but we have to invert the
predicate to choose the other source instead.
This removes 5 extra moves of constants in nexuiz shaders. No
statistically significant performance difference on my Sandybridge
laptop (n=5).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 811c147220d2630b769e505ce4d40ef9108fe034 |
|
09-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Constant-fold immediates in src0 of CMP instructions.
This is like what we do with add/mul, but we also have to flip the
conditional test.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 963431829055f63ec94d88c97a5d07d30e49833a |
|
03-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Remove broken optimization for live intervals in loops.
The theory here was to detect a temporary variable used within a loop,
and avoid considering it live across the entire loop. However, it was
overeager and failed when the first definition of the variable
appeared within the loop but was only conditionally defined.
Fixes glsl-fs-loop-redundant-condition.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 5d7fefb9afbcc6f1d58a92d07c390e6b912c3b00 |
|
03-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Switch W and 1/W in Sandybridge interpolation setup.
Various documentation mentions that "W" is handed to the WM stage,
but further digging seems to indicate that they really mean 1/W.
The code here is still unclear, but changing this fixes piglit
test "fragcoord_w" on Sandybridge as well as a Khronos ES2 conformance
test. I also tested 3DMarkMobile ES2.0's taiji and hoverjet demos, as
well as Nexuiz, just to be safe.
NOTE: This is a candidate for the 7.10 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a99e80d795f7c6aec0e73369a31d1728577b9727 |
|
25-Mar-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Fix ugly indentation left from previous commit
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 89d81ab16c05818b290ed735c1343d3abde449bf |
|
25-Jan-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
glsl: Calcluate Mesa state slots in front-end instead of back-end
This should be the last bit of infrastructure changes before
generating GLSL IR for assembly shaders.
This commit leaves some odd code formatting in ir_to_mesa and brw_fs.
This was done to minimize whitespace changes / reindentation in some
loops. The following commit will restore formatting sanity.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 252eaa765e69a70036ec33a7e1e0ffeac1aab2ff |
|
29-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Avoid name clash of loop counter and member
src/mesa/drivers/dri/i965/brw_fs.cpp:565 warning: name lookup of ‘c’ changed
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 0c8beb0ab5e72a9d2ecaad51db16a7d5291e120b |
|
27-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Fix linear gl_Color interpolation on pre-gen6 hardware.
Civilization 4's shaders make heavy use of gl_Color and don't use
perspective interpolation. This resulted in rivers, units, trees, and
so on being rendered almost entirely white. This is a regression
compared to the old fragment shader backend.
Found by inspection (comparing the old and new FS backend code).
References: https://bugs.freedesktop.org/show_bug.cgi?id=32949
NOTE: This is a candidate for the 7.10 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4e994e150f65c854229b4af12eae5519ebd9dda1 |
|
25-Mar-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
i965/fs: Use different name for inner loop counter
'i' is already used for the outer loop. This caused some problems
while doing other work in this area. No bug exists here... until you
want to use the outer loop counter in the inner loop.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 2911fa0cca86f7acbc5423cab4dd328a412253cd |
|
13-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Make compile failure more verbose with INTEL_DEBUG=wm.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4a101f957714dea2bc956d516d34c5b56ecb2c64 |
|
13-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Clean up reg_undef args from long ago lack of fs_inst overloads.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 53d78be3bde68bfb6416fb9c1abfbc24030f390e |
|
13-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Clean up the emit calls by introducing emit() overload helpers.
I think the code ends up a lot more legible this way, though we've
still got the overloads in the fs_inst as well (even though there's
only one caller left currently).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 5e9aa9926b9bdf1260ce7350b88908bda337388b |
|
26-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
mesa: Remove the CompileShader driver hook; it's just a no-op.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 2279156fe7ac9718533b8b0de90ae96100486680 |
|
16-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename brw_(IF|CONT)_gen6 functions to gen6_(IF|CONT).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| cc48d663f7282411d88c6187ce3d03f21df0acd3 |
|
16-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename BRW_SAMPLER_MESSAGE_..._GEN5 to GEN5_SAMPLER_MESSAGE.
We already have lots of GEN6_* defines; this seems more consistent.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a99447314ca1cfce60f2a22285398fb222b2a440 |
|
12-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix alpha testing when there is no color buffer in the FBO.
We were alpha testing against an unwritten value, resulting in garbage.
(part of) Bug #35073.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| b60651a17ba85af14e9d7b9a1398e065adb58665 |
|
11-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965: Do our lowering passes before the loop of optimization.
The optimization loop won't reinsert noise instructions or quadop
vectors, so we were traversing the tree for nothing. Lowering vector
indexing was in the loop after do_common_optimization() to avoid the
work if it ended up that the index was actually constant, but that has
been called already in the core.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 25e31140952c328f70f804e0134664d7ed6248a6 |
|
14-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Enable texture lookups whose return type is 'float'
This enables the new shadow texture functions in GLSL 1.30.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 403be1111190a3fe63ae03bc0111e0a0b026495b |
|
13-Mar-2011 |
Eric Anholt <eric@anholt.net> |
Revert "i965: Use the fixed function GLSL program instead of the ARB program."
This reverts commit 81b34a4e3a7aec9cdf2781757408dc5e9eec79cb. There
were regressions in the core change that this depends on.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 81b34a4e3a7aec9cdf2781757408dc5e9eec79cb |
|
12-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use the fixed function GLSL program instead of the ARB program.
This gets one more piece of the pipeline onto the new codegen backend.
Once ARB_fragment_program can generate GLSL programs, we can nuke the
old backend.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 186d3bc7a3389b78a851e34d8f970c28b8db1608 |
|
01-Mar-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
Revert "i965/fs: Correctly set up gl_FragCoord.w on Sandybridge."
This reverts commit 4a3b28113c3d23ba21bb8b8f5ebab7c567083a6d, as it
caused a regression on Ironlake (bug #34646).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 58f7c9c72ee52527610b26ca8a137dd88c082c89 |
|
25-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Initial plumbing to support TXD.
This adds the opcode and the code to convert ir_txd to OPCODE_TXD;
it doesn't actually add support yet.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 2830b1ae9032666e62460de5aece8db843c51c14 |
|
28-Oct-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Complete TXL support on gen5+.
Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was
never handled.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4ddd11aad6a396e98ae30e3e78f6736804eae541 |
|
28-Oct-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Complete TXL support on gen4.
Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was
never handled.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| e54d62b89677624b5806442cc5053c0ceedd79b0 |
|
28-Oct-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Use a properly named constant in TXB handling.
The old value, BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE makes it sound like we're
doing a non-bias texture lookup. It has the same value as the new constant
BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE, so there should be no
functional changes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4a3b28113c3d23ba21bb8b8f5ebab7c567083a6d |
|
20-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Correctly set up gl_FragCoord.w on Sandybridge.
pixel_w is the final result; wpos_w is used on gen4 to compute it.
NOTE: This is a candidate for the 7.10 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| df2aef0e197f9276f60a8e755260420c90841269 |
|
20-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Refactor control flow stack handling.
We can't safely use fixed size arrays since Gen6+ supports unlimited
nesting of control flow.
NOTE: This is a candidate for the 7.10 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 2c2686b912de19a430aba9f5ea5fa679eabdc5c6 |
|
19-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Avoid register coalescing away gen6 MATH workarounds.
The code that generates MATH instructions attempts to work around
the hardware ignoring source modifiers (abs and negate) by emitting
moves into temporaries. Unfortunately, this pass coalesced those
registers, restoring the original problem. Avoid doing that.
Fixes several OpenGL ES2 conformance failures on Sandybridge.
NOTE: This is a candidate for the 7.10 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 72cd7e87d35e96fad9643f1cee706a8568fa3fa1 |
|
19-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Apply source modifier workarounds to POW as well.
Single-operand math already had these workarounds, but POW (the only two
operand function) did not. It needs them too - otherwise we can hit
assertion failures in brw_eu_emit.c when code is actually generated.
NOTE: This is a candidate for the 7.10 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 0f7325b89038937bd428f7c89ed9859189a0ab0b |
|
27-Dec-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Emit texel offsets in sampler messages.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| d3073f58c17d8675a2ecdd5dfa83e5520c78e1a8 |
|
21-Jan-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
Convert everything from the talloc API to the ralloc API.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| e256e4743c3f8f924f0d191759d9428f33f3e329 |
|
19-Jan-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
glsl, i965: Remove unnecessary talloc includes.
These are already picked up by ir.h or glsl_types.h.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 382c2d99da3f219a5b82f391a81b534b6b44ebce |
|
19-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add a helper function for detecting math opcodes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 1991d92207cf629ba4ceead4bfc3f768d7b9e402 |
|
19-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Assign URB/CURB register numbers after instruction scheduling.
This fixes a bunch of unnecessary barriers due to the scheduler not
knowing what that arbitrary register description refers to when trying
to reason about its dependencies.
The result is rescheduling in the convolution kernel shader in
Lightsmark, which results in avoiding register spilling and increasing
the performance of the first scene from 6-7 fps midway through the
panning to 11fps. The register spilling was a regression from Mesa
7.9 to Mesa 7.10.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 63879d90ace519749fed228ca0e21b5b56c7e1c0 |
|
19-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add an instruction scheduler.
Improves performance of my GLSL demo by 5.1% (+/- 1.4%, n=7). It also
reschedules the giant multiply tree at the end of
glsl-fs-convolution-1 so that we end up not spilling registers,
producing the expected level of performance.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 3f2fe31eee1667ef9cad99aaad69e52a09c9effa |
|
19-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add a helper for detecting texturing opcodes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 568e0083651dd29e5bce94ade8625a64a0e85e88 |
|
18-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix a comment typo.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 8ce425f3e3e330bda859c439b915c4e59b1a2bf4 |
|
18-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix a bug in i965 compute-to-MRF.
Fixes piglit glsl-fs-texture2d-branching. I couldn't come up with a
testcase that didn't involve dead code, but it's still worthwhile to
fix I think.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| e4be665bbddcb6ddfd7b9b13f01152a97097b35c |
|
18-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix dead pointers to fp->Parameters->ParameterValues[] after realloc.
Fixes texrect-many regression with ff_fragment_shader -- as we added
refs to the subsequent texcoord scaling paramters, the array got
realloced to a new address while our params[] still pointed at the old
location.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a6e4614ca1284c5731876bb88732b326bf13aba0 |
|
14-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965: Replace broken handling of dead code with an assert.
This code should never have been triggered, but I often did anyway
when I disabled optimization passes during debugging, then spent my
time debugging that this code doesn't work.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 7c7df146b59bae9dcb3a271bd3c671e273015617 |
|
14-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add an invalidation of live intervals after register splitting.
No effect, since it was called before live intervals were calculated.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| c3f000b3926988124a44ce7e8cd6588e46063058 |
|
12-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Do flat shading when appropriate.
We were trying to interpolate, which would end up doing unnecessary
math, and doing so on undefined values. Fixes glsl-fs-flat-color.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| e880a57a71bbd5152ed26367dcc7051f21c20981 |
|
12-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965: Clarify when we need to (re-)calculate live intervals.
The ad-hoc placement of recalculation somewhere between when they got
invalidated and when they were next needed was confusing. This should
clarify what's going on here.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| ab56e3be9aae54602372427755305c354821e105 |
|
12-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: When producing ir_unop_abs of an operand, strip negate.
We were returning the negative absolute value, instead of the absolute
value. Fixes glsl-fs-abs-neg.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4eb7284ef98c24331761cbe683c5bd89058e3ad3 |
|
12-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965: Tighten up the check for flow control interfering with coalescing.
This greatly improves codegen for programs with flow control by
allowing coalescing for all instructions at the top level, not just
ones that follow the last flow control in the program.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| df4d83dca4618eb7077637865763d3e9ab750d11 |
|
29-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Do lowering of array indexing of a vector in the FS.
Fixes a regression in ember since switching to the native FS backend,
and the new piglit tests glsl-fs-vec4-indexing-{2,3} for catching this.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 54df8e48bcceacbfa468d5237f2981b26493df29 |
|
28-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix regression in FS comparisons on original gen4 due to gen6 changes.
Fixes 26 piglit cases on my GM965.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 74dffb39c3434b590b36833905f2b12a6e3477e9 |
|
28-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Factor out the ir comparision to BRW_CONDITIONAL_* code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 634a7dce9c1d9e4a8576ff8197c8adaea7e9ddd1 |
|
27-Dec-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Flatten if-statements beyond depth 16 on pre-gen6.
Gen4 and Gen5 hardware can have a maximum supported nesting depth of 16.
Previously, shaders with control flow nested 17 levels deep would
cause a driver assertion or segmentation fault.
Gen6 (Sandybridge) hardware no longer has this restriction.
Fixes fd.o bug #31967.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4374703a9b2ce0be105ee544c8402a932e3e1f52 |
|
22-Dec-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: explicit tell header present for fb write on sandybridge
Determine header present for fb write by msg length is not right
for SIMD16 dispatch, and if there're more output attributes, header
present is not easy to tell from msg length. This explicitly adds
new param for fb write to say header present or not.
Fixes many cases' hang and failure in GL conformance test.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 036c817f77f71e7c4b17571ae100a9bc93d8fe5b |
|
13-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix gl_FragCoord.z setup on gen6.
Fixes glsl-bug-22603.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| c3ca384e7190656afcd9f5143e811843efa2b3cb |
|
09-Dec-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Silence uninitialized variable warning.
Fixes this GCC warning.
brw_fs.cpp: In function 'brw_reg brw_reg_from_fs_reg(fs_reg*)':
brw_fs.cpp:3255: warning: 'brw_reg' may be used uninitialized in this function
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| b2167a6c013c057e731b96486e3363c1d1171d60 |
|
08-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix flipped value of the not-embedded-in-if on gen6.
Fixes:
glean/glsl1-! (not) operator (1, fail)
glean/glsl1-! (not) operator (1, pass)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 7ca7e9b626389dd6dac683c6664b8478e6d5c3b9 |
|
07-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Work around gen6 ignoring source modifiers on math instructions.
With the change of extended math from having the arguments moved into
mrfs and handed off through message passing to being directly hooked
up to the EU, it looks like the piece for doing source modifiers
(negate and abs) was left out.
Fixes:
fog-modes
glean/fp1-ARB_fog_exp test
glean/fp1-ARB_fog_exp2 test
glean/fp1-Computed fog exp test
glean/fp1-Computed fog exp2 test
ext_fog_coord-modes
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 6848e27e1462e98dd91826a06f96c203c9eeebd0 |
|
07-Dec-2010 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Correctly emit constants for aggregate types (array, matrix, struct)
Previously the code only handled scalars and vectors. This new code
is modeled somewhat after similar code in ir_to_mesa.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 16f8c823898fd71a3545457eacd2dc31ddeb3592 |
|
11-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Move payload reg setup to compile, not lookup time.
Payload reg setup on gen6 depends more on the dispatch width as well
as the uses_depth, computes_depth, and other flags. That's something
we want to decide at compile time, not at cache lookup. As a bonus,
the fragment shader program cache lookup should be cheaper now that
there's less to compute for the hash key.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 843a6a308e05bd4bf2056e08ec65ac4770097b93 |
|
01-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gen6 CONTINUE instruction emit.
At this point, piglit tests for fragment shader loops are working.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 00e5a743e2ee3981a34b95067a97fa73c0f5d779 |
|
01-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gen6 BREAK ISA emit.
There are now two targets: the hop-to-end-of-block target, and the
target for where to resume execution for active channels.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4890e0f09c934e3ffb692b417e5444e43685c876 |
|
01-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gen6 DO/WHILE ISA emit.
There's no more DO since there's no more mask stack, and WHILE has
been shuffled like IF was.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 2927b6c21202fd0f9a661665e0093e7193c5df6e |
|
30-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix type of gl_FragData[] dereference for FB write.
Fixes glsl-fs-fragdata-1, and hopefully Eve Online where I noticed
this bug in the generated shader. Bug #31952.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| b6b91fa02911f5dfc5d528d822674ee5557800d9 |
|
19-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove duplicate MRF writes in the FS backend.
This is quite common for multitexture sampling, and not only cuts down
on the second and later set of MOVs, but typically also allows
compute-to-MRF on the first set.
No statistically siginficant performance difference in nexuiz (n=3),
but it reduces instruction count in one of its shaders and seems like
a good idea.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 47b1aac1cf0aefae4df58a60bb7eb26d21e25913 |
|
18-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Improve compute-to-mrf.
We were skipping it if the instruction producing the value we were
going to compute-to-mrf used its result reg as a source reg. This
meant that the typical "write interpolated color to fragment color" or
"texture from interpolated texcoord" shader didn't compute-to-MRF.
Just don't check for the interference cases until after we've checked
if this is the instruction we wanted to compute-to-MRF.
Improves nexuiz high-settings performance on my laptop 0.48% +- 0.08%
(n=3).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 19631fab35ca4d5ca64d606922f3f20774b27645 |
|
19-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Recognize saturates and turn them into a saturated mov.
On pre-gen6, this turns 4 instructions into 1. We could still do
better by folding the saturate into the instruction generating the
value if nobody else uses it, but that should be a separate pass.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 602ae2441aaca6a652d3fc78114bb60852132f98 |
|
18-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fold constants into the second arg of BRW_SEL as well.
This hits a common case with min/max operations.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| f9b420d3bda25ea517b66c5ee2c6bde4fdff3935 |
|
18-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove extra \n at the end of every instruction in INTEL_DEBUG=wm.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 61126278a39fbff9a66aff9ecc37893e87950091 |
|
19-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix compute_to_mrf to not move a MRF write up into another live range.
Fixes glsl-fs-copy-propagation-texcoords-1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 63684a9ae7a66f68df1f2c68cd9358e5622122a3 |
|
19-Nov-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
glsl: Combine many instruction lowering passes into one.
This should save on the overhead of tree-walking and provide a
convenient place to add more instruction lowering in the future.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 11d6f1c69871d0b7edc28f639256460839fccd2d |
|
16-Nov-2010 |
Ian Romanick <ian.d.romanick@intel.com> |
glsl: Add ir_quadop_vector expression
The vector operator collects 2, 3, or 4 scalar components into a
vector. Doing this has several advantages. First, it will make
ud-chain tracking for components of vectors much easier. Second, a
later optimization pass could collect scalars into vectors to allow
generation of SWZ instructions (or similar as operands to other
instructions on R200 and i915). It also enables an easy way to
generate IR for SWZ instructions in the ARB_vertex_program assembler.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| fc92e87b9757eda01caf0bb3e2c31b1dbbd73aa0 |
|
11-Nov-2010 |
Ian Romanick <ian.d.romanick@intel.com> |
glsl: Eliminate assumptions about size of ir_expression::operands
This may grow in the near future.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| f2616e56de8a48360cae8f269727b58490555f4d |
|
18-Nov-2010 |
Ian Romanick <ian.d.romanick@intel.com> |
glsl: Add ir_unop_sin_reduced and ir_unop_cos_reduced
The operate just like ir_unop_sin and ir_unop_cos except that they
expect their inputs to be limited to the range [-pi, pi]. Several
GPUs require this limited range for their sine and cosine
instructions, so having these as operations (along with a to-be-written
lowering pass) helps this architectures.
These new operations also matche the semantics of the
GL_ARB_fragment_program SCS instruction. Having these as operations
helps in generating GLSL IR directly from assembly fragment programs.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 50b4508319cc5277d51a38065850eaa092afc0d4 |
|
18-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Eliminate dead code more aggressively.
If an instruction writes reg but nothing later uses it, then we don't
need to bother doing it. Before, we were just killing code that was
never read after it was ever written.
This removes many interpolation instructions for attributes with only
a few comopnents used. Improves nexuiz high-settings performance .46%
+/- .12% (n=3) on my Ironlake.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| da35388044db4aa6fc66c08a087d8d703b5a6008 |
|
17-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fail on loops on gen6 for now until we write the EU emit code for it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| d512cbf58f9039575dbbb5ab65dbbf7b742a0854 |
|
17-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Shut up spurious gcc warning about GLSL_TYPE enums.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 9935fe705df44bb633039ca74332cc0c126ccc30 |
|
17-Nov-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
glsl: Remove the ir_binop_cross opcode.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 3b337f5cd94384d2d5918fb630aa8089e49b1d8d |
|
13-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix gl_FragCoord inversion when drawing to an FBO.
This showed up as cairo-gl gradients being inverted on everyone but
Intel, where I'd apparently tweaked the transformation to work around
the bug. Fixes piglit fbo-fragcoord.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| d11db2a857141c556378fde9f9f5ec08c7f8636f |
|
14-Nov-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Silence uninitialized variable warning.
Silences this GCC warning.
brw_fs.cpp: In member function 'void fs_visitor::split_virtual_grfs()':
brw_fs.cpp:2516: warning: unused variable 'reg'
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 9effc1adf1e7ba57fb3b10909762b76c1ae12f61 |
|
12-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: re-enable gen6 IF statements in the fragment shader.
IF statements were getting flattened while they were broken. With
Zhenyu's last fix for ENDIF's type, everything appears to have lined
up to actually work.
This regresses two tests:
glsl1-! (not) operator (1, fail)
glsl1-! (not) operator (1, pass)
but fixes tests that couldn't work before because the IFs couldn't be
flattened:
glsl-fs-discard-01
occlusion-query-discard
(and, naturally, this should be a performance improvement for apps
that actually use IF statements to avoid executing a bunch of code).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| cbc966b57bdb61f5bc158352a9c8dd57bf31b81e |
|
19-Oct-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add bit operation support to the fragment shader backend.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 9e3641bd0d739a87a6998300ca29580cb557f380 |
|
25-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Make FS uniforms be the actual type of the uniform at upload time.
This fixes some insanity that would otherwise be required for GLSL
1.30 bit ops or gen6 integer uniform operations in general, at the
cost of upload-time pain. Given that we only have that pain because
mesa's mangling our integer uniforms to be floats, this something that
should be fixed outside of the shader codegen.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 84eba3ef71dfa822e5ff0463032cdd2e3515b888 |
|
13-Oct-2010 |
Ian Romanick <ian.d.romanick@intel.com> |
Track separate programs for each stage
The assumption is that all stages are the same program or that
varyings are passed between stages using built-in varyings.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 62452e7d94a6353b59dfe0a8891d0709670dbeac |
|
26-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for discard instructions on gen6.
It's a little more painful than before because we don't have the handy
mask register any more, and have to make do with cooking up a value
out of the flag register.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 0e8c834ffa2f6d943a927e1a32a273d2f8600694 |
|
26-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Clear some undefined fields of g0 when using them for gen6 FB writes.
This doesn't appear to help any testcases I'm looking at, but it looks
like it's required.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 07cd8f46acc34b04308f81de2faf05ba33da264b |
|
22-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for pull constants to the new FS backend.
Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| ff622d5528c8cca465e29081c0792ca210cdd092 |
|
22-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Move the FS disasm/annotation printout to codegen time.
This makes it a lot easier to track down where we failed when some
code emit triggers an assert. Plus, less memory allocation for
codegen.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 1d91f8d9164b38b4c924f43ec4fc5ceb65c96a78 |
|
22-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Be more aggressive in tracking live/dead intervals within loops.
Fixes glsl-fs-convolution-2, which was blowing up due to the array
access insanity getting at the uniform values within the loop. Each
temporary was considered live across the whole loop.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4e7252510976d8d3ff12437ea8842129f24d88f5 |
|
22-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Correct scratch space allocation.
One, it was allocating increments of 1kb, but per thread scratch space
is a power of two. Two, the new FS wasn't getting total_scratch set
at all, so everyone thought they had 1kb and writes beyond 1kb would
go stomping on a neighbor thread.
With this plus the previous register spilling for the new FS,
glsl-fs-convolution-1 passes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 99b2c8570ea6f46c6564681631f0e0750a0641cc |
|
19-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for register spilling.
It can be tested with if (0) replaced with if (1) to force spilling for all
virtual GRFs. Some simple tests work, but large texturing tests fail.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 7a3f113e79f983222ecc95c33655a8c9354fcfad |
|
21-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix gl_FrontFacing emit on pre-gen6.
It's amazing this code worked. Basically, we would get lucky in
register allocation and the tests using frontfacing would happen to
allocate gl_FrontFacing storage and the instructions generating
gl_FrontFacing but pointing at another register to the same hardware
register. Noticed during register spilling debug, when suddenly they
didn't get allocatd the same storage.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 5ac6c4ecfe77bf7e02ae61981b2c8b1fe73027cd |
|
20-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Split register allocation out of the ever-growing brw_fs.cpp.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| ae5698e60467db2a7e3f730788cdcdd3711da101 |
|
19-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use the new style of IF statement with embedded comparison on gen6.
"Everyone else" does it this way, so follow suit. It's fewer
instructions, anyway.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 80c9f756b28d15ca097963af35915f5b073f081d |
|
19-Oct-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove unused variable.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 746e68c50b4ae1566b342fbc965557b6dbcfaa2e |
|
18-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix a weirdness in NOT handling.
XOR makes much more sense. Note that the previous code would have
failed for not(not(x)), but that gets optimized out.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| ea213417f14a8b2734cb2a88d8aa1ac05a70b7d5 |
|
18-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Disable the debug printf I added for FS disasm.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 65d4234c2398aaa48eb5e29e6e7bede40fe2fd36 |
|
18-Oct-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add missing "break" statement.
Otherwise, it would try to handle arrays as structures, use
uninitialized memory, and crash.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 81d0a1fb3f1e5b7bcf43145f8a096691e3a5fdfb |
|
15-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set the type of the null register to fix gen6 FS comparisons.
We often use reg_null as the destination when setting up the flag
regs. However, on gen6 there aren't general implicit conversions to
destination types from src types, so the comparison to produce the
flag regs would be done on the integer result interpreted as a float.
Hilarity ensued.
Fixes 20 piglit cases.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 20b39c7760487bae73489b9812408e12d1d56dd5 |
|
15-Oct-2010 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Fix indentation after commit 3322fbaf
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 3322fbaf3b5e305ce00c1d08c26965bb98e0cef0 |
|
14-Oct-2010 |
Ian Romanick <ian.d.romanick@intel.com> |
glsl: Slightly change the semantic of _LinkedShaders
Previously _LinkedShaders was a compact array of the linked shaders
for each shader stage. Now it is arranged such that each slot,
indexed by the MESA_SHADER_* defines, refers to a specific shader
stage. As a result, some slots will be NULL. This makes things a
little more complex in the linker, but it simplifies things in other
places.
As a side effect _NumLinkedShaders is removed.
NOTE: This may be a candidate for the 7.9 branch. If there are other
patches that get backported to 7.9 that use _LinkedShader, this patch
should be cherry picked also.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4b4284c9c9b472f750663352485290c22f8c3921 |
|
15-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix texturing on pre-gen5.
I broke it in 06fd639c519214b6ebcbf29127b6d9ed429f8641 by only testing
2 generations of hardware :(
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| f157812bbbcf9caac1f84988e738fc9d1e051056 |
|
14-Oct-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add support for ir_unop_round_even via the RNDE instruction.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a81d423d93f22a948f3aa4bf73dc6b1a3b70192f |
|
14-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Enable the new FS backend on pre-gen6 as well.
It is now to the point where we have no regressing piglit tests. It
also fixes Yo Frankie! and Humus DynamicBranching, probably due to the
piglit bias tests that work that didn't on the Mesa IR backend.
As a downside, performance takes about a 5-10% performance hit at the
moment (e.g. nexuiz 19.8fps -> 18.8fps), which I plan to resolve by
reintroducing 16-wide fragment shaders where possible. It is a win,
though, for fragment shaders using flow control.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| f541b685aaf404fa7c8142f51d91c2720d82f264 |
|
14-Oct-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use RNDZ for ir_unop_trunc in the new FS.
The existing code used RNDD, which rounds down, rather than toward zero.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| c4226142f3b5d1c931fcc781be8a3aafdfabf316 |
|
14-Oct-2010 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use logical-not when emitting ir_unop_ceil.
Fixes piglit test glsl-fs-ceil.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 5dd07b442e02696bf0ec5d4e3b4be1674519664a |
|
14-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add peepholing of conditional mod generation from expressions.
This cuts usually 2 out of 3 instructions for flag reg generation (if
statements, conditional assignment) by producing the conditional mod
in the expression representing the boolean value.
Fixes glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined (register
allocation no longer fails for the conditional generation
proliferation)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| d5599c0b6a22cd0bbc475ec715824660144d02a0 |
|
14-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add a function for handling the move of boolean values to flag regs.
This will be a place to peephole comparisions directly to the flag
regs, and for now avoids using MOV with conditional mod on gen6, which
is now illegal.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4f88550ba0e1ad07e39903f268975921c0101e85 |
|
14-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add a pass to the FS to split virtual GRFs to float channels.
Improves nexuiz performance 0.91% (+/- 0.54%, n=8)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| b8613d70da34217b98edb9ac9e0a4c9a6598d0b3 |
|
14-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Update the live interval when coalescing regs.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 0c6752026c405dc3ab5fe85c6a40ac3f04c685c3 |
|
14-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set class_sizes[] for the aligned reg pair class.
So far, I've only seen this be a valgrind warning and not a real failure.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a57ef244fc55476660f9fb76982130c5c0b25163 |
|
14-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for rescaling GL_TEXTURE_RECTANGLE coords to new FS.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 080e7aface81e6a055ac61988ca27a88ad70f879 |
|
12-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix missing "break;" in i2b/f2b, and missing AND of CMP result.
Fixes glsl-fs-i2b.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| bcec03d527561e2df56bf9ebfa250cef56bb732b |
|
12-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Always use the new FS backend on gen6.
It's now much more correct for gen6 than the old backend, with just 2
regressions I've found (one of which is common with pre-gen6 and will
be fixed by an array splitting IR pass).
This does leave the old Mesa IR backend getting used still when we
don't have GLSL IR, but the plan is to get GLSL IR input to the driver
for the ARB programs and fixed function by the next release.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 0cadd32b6dc80455802c04b479ec8e768f93ffe1 |
|
12-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix gen6 pixel_[xy] setup to avoid mixing int and float src operands.
Pre-gen6, you could mix int and float just fine. Now, you get goofy
results.
Fixes:
glsl-arb-fragment-coord-conventions
glsl-fs-fragcoord
glsl-fs-if-greater
glsl-fs-if-greater-equal
glsl-fs-if-less
glsl-fs-if-less-equal
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 720ed3c906b0f6d5822fe9fa442294c9828e1560 |
|
11-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Expand uniform args to gen6 math to full registers to get hstride == 1.
This is a hw requirement in math args. This also is inefficient, as
we're calculating the same result 8 times, but then we've been doing
that on pre-gen6 as well. If we're doing math on uniforms, though,
we'd probably be better served by having some sort of mechanism for
precalculating those results into another uniform value to use.
Fixes 7 piglit math tests.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 317dbf4613ebf56ca14ee70c1ad6e620ad7942c2 |
|
11-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't compute-to-MRF in gen6 math instructions.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 25cf241540007088936a6df16c849441087f722c |
|
11-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't consider gen6 math instructions to write to MRFs.
This was leftover from the pre-gen6 cleanups. One tests regresses
where compute-to-MRF now occurs.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| c6dbf253d284f68b0d0e4a3c145583880855324b |
|
08-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Compute to MRF in the new FS backend.
This didn't produce a statistically significant performance difference
in my demo (n=4) or nexuiz (n=3), but it still seems like a good idea
and is recommended by the HW team.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 06fd639c519214b6ebcbf29127b6d9ed429f8641 |
|
09-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Give the FB write and texture opcodes the info on base MRF, like math.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 0cd6cea8a3e9339fc69f9de0da6b40e4f9d5f4fe |
|
08-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Give the math opcodes information on base mrf/mrf len.
This is progress towards enabling a compute-to-MRF pass.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 37758fb1cbb1ddcd106553763c1b1f222f4cfb47 |
|
11-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Move FS backend structures to a header.
It's time to start splitting some of this up.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 251fe2785484f7ba0c194c92fe0feff9c78b52ca |
|
10-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Reduce register interference checks for changed FS_OPCODE_DISCARD.
While I don't know of any performance changes from this (once extra
reg available out of 128), it makes the generated asm a lot cleaner
looking.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 90c402204018c78f4a0b8a79515cf8c582092963 |
|
10-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Split FS_OPCODE_DISCARD into two steps.
Having the single opcode write then read the reg meant that single
instruction opcodes had to consider their source regs to interfere
with their dest regs.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| c52a0b5c7d4b55fb183c8ab68aa3561432287283 |
|
05-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add register coalescing to the new FS backend.
Improves performance of my GLSL demo 14.3% (+/- 4%, n=4) by
eliminating the moves used in ir_assignment and ir_swizzle handling.
Still 16.5% to go to catch up to the Mesa IR backend, presumably
because instructions are almost perfectly mis-scheduled now.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| cac04a93974e7ae773b84e000a2b26391ee2f4bb |
|
08-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix new FS gen6 interpolation for sparsely-populated arrays.
We'd overwrite the same element twice.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| bbb840049e7a92af6e0e8c2c5c21c63caec9e826 |
|
06-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Normalize cubemap coordinates like is done in the Mesa IR path.
Fixes glsl-fs-texturecube-2-*
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4d202da7a4951eb534f77014238e7cdca9f781e9 |
|
07-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Disable emitting if () statements on gen6 until we really fix them.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| b380531fd40e0876218b1116502bafea7911bd3d |
|
06-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't assume that WPOS is always provided on gen6 in the new FS.
We sensibly only provide it if the FS asks for it. We could actually
skip WPOS unless the FS needed WPOS.zw, but that's something for
later.
Fixes: glsl-texture2d and probably many others.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 1fdc8c007ea66b4c9866bf2c679653a005307fa5 |
|
06-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gl_FrontFacing on gen6.
Fixes glsl1-gl_FrontFacing var (2) with new FS.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a760b5b509f85991a10400977576afabcedbb3c5 |
|
06-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Refactor gl_FrontFacing setup out of general variable setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 75270f705f319b0ecf297d1bdd328e52a8a956aa |
|
06-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Gen6's sampler messages are the same as Ironlake.
This should fix texturing in the new FS backend.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| fe6efc25ed3c1edf26073c4e6b6a3a45c857c1eb |
|
06-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't do 1/w multiplication in new FS for gen6
Not needed now that we're doing barycentric.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 5eeaf3671e2f913d38187fd1401c4b22a2900d57 |
|
06-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix botch in the header_present case in the new FS.
I only set it on the color_regions == 0 case, missing the important
case, causing GPU hangs on pre-gen6.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 3c97c00e3810d31c3aa26173eb9fdef91b3e7c87 |
|
06-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add back gen6 headerless FB writes to the new FS backend.
It's not that hard to detect when we need the header.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 634abbf7b2e6ea21db30aafc0de9472ee31d4173 |
|
05-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Also do constant propagation for the second operand of CMP.
We could do the first operand as well by flipping the comparison, but
this covered several CMPs in code I was looking at.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| dcd0261affc293b75d231e612091ec7b1076fff6 |
|
05-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Enable the constant propagation code.
A debug disable had slipped in.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| ea909be58dda7e916cb9ce434ecb78597881ad33 |
|
05-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gen6 FB writes to the new FS.
This uses message headers for now, since we'll need it for MRT. We
can cut out the header later.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 3bf8774e9c293fcad654d1bd67d4b43247b82f97 |
|
04-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add initial folding of constants into operand immediate slots.
We could try to detect this in expression handling and do it
proactively there, but it seems like less logic to do it in one
optional pass at the end.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| e27c88d8e6c9d18bfa793f884d02ce6011c4bdde |
|
04-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add trivial dead code elimination in the new FS backend.
The glsl core should be handling most dead code issues for us, but we
generate some things in codegen that may not get used, like the 1/w
value or pixel deltas. It seems a lot easier this way than trying to
work out up front whether we're going to use those values or not.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 9faf64bc32cf7c1a06a302fff9f80d7e2e2685d5 |
|
04-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Be more conservative on live interval calculation.
This also means that our intervals now highlight dead code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4fb0c92c6986cf4e88296bab8837320210f1794f |
|
03-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for EXT_texture_swizzle to the new FS backend.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 64a9fc3fc15603a8e25d0e1146fe5da5a5bde55b |
|
02-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't try to emit code if we failed register allocation.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 6397addd6146661689a0e315b06e543ef12d8868 |
|
02-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix off-by-ones in handling the last members of register classes.
Luckily, one of them would result in failing out register allocation
when the other bugs were encountered. Applies to
glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined, which still
fails register allocation, but now legitimately.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| afb64311e3484002e06aeac62187b68467610449 |
|
02-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add a sanity check for register allocation sizes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 5ee09413162f4ec83cc7a738e807ffde8c89cca7 |
|
02-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: When producing a single channel swizzle, don't make a temporary.
This quickly cuts 8% of the instructions in my glsl demo.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a0799725f52386cef911d3e104c5514a2811290b |
|
02-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Restore the forcing of aligned pairs for delta_xy on chips with PLN.
By doing so using the register allocator now, we avoid wasting a
register to make the alignment happen.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| e9bcc8328968f05a5688a020bfa8165260865a9b |
|
01-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up copy'n'pasteo from moving coordinate setup around for gen4.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| bfd9715c3c9d40b3f937638073ff2f0969ebd143 |
|
01-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add real support for pre-gen5 texture sampling to the new FS.
Fixes 36 testcases, including glsl-fs-shadow2d*-bias which fail on the
Mesa IR backend.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 8f63a44636e4fef2f35fe73f24c27db9b04389b1 |
|
01-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Pre-gen6, map VS outputs (not FS inputs) to URB setup in the new FS.
We should fix the SF to actually give us just the data we need, but
this fixes regressions in the new FS until then.
Fixes:
glsl-kwin-blur
glsl-routing
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| ff5ce9289b5159e7de34706b31be771d3e3cefd6 |
|
01-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Also increment attribute location when skipping unused slots.
Fixes glsl1-texcoord varying.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 354c40a62411262d1223f439fdaf2176ca9adbe9 |
|
01-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix the gen6 jump size for BREAK/CONT in new FS.
Since gen5, jumps are in increments of 64 bits instead of increments
of 128-bit instructions.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| efc4a6f7909dbf554ee440210233c4b0f89ac89e |
|
01-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add gen6 attribute interpolation to new FS backend.
Untested, since my hardware is not booting at the moment.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 1d073cb2d920d1c0b8c6d598055b14048fedc96e |
|
01-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Split the gen4 and gen5 sampler handling apart.
Trying to track the insanity of the different argument layouts for
normal/shadow crossed with normal/lod/bias one generation at a time is
enough.
Fixes: glsl1-texture2D() with bias.
(first test passing in this code that doesn't pass without it!)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 5f237a1ccb28399fbbceecea694f5d18ebba9938 |
|
01-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use the lowering pass for texture projection.
We should end up with the same code, but anyone else with this issue
could share the handling (which I got wrong for shadow comparisons in
the driver before).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| c6960e4471abe287448b9d0e7e6519d588cdf43c |
|
30-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix new FS handling of builtin uniforms with packed scalars in structs.
We were pointing each element at the .x channel of the
ParameterValues.
Fixes glsl1-linear fog.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 6f6542a483ec726538f8a4555bddaeb0be6b2146 |
|
30-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix whole-structure/array assignment in new FS.
We need to walk the type tree to get the right register types for
structure components. Fixes glsl-fs-statevar-call.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| ad1506c5ac61b75e45f24a2e18c91dc8a49a3bb0 |
|
30-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove my "safety counter" code from loops.
I've screwed this up enough times that I don't think it's worth it.
This time, it was that I was doing it once per top-level body
instruction instead of just once at the end of the loop body.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| b90c7d1713c5a52fd85cb9dacad5828ae2fdbf6c |
|
30-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add live interval analysis and hook it up to the register allocator.
Fixes 13 piglit cases that failed at register allocation before.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| e1261d3c493ff48348483a0084f3017c7e663dc0 |
|
29-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: First cut at register allocation using graph coloring.
The interference is totally bogus (maximal), so this is equivalent to
our trivial register assignment before. As in, passes the same set of
piglit tests.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 21148e1c0a3cf9cf25ded006a3d5ce2b12803ea9 |
|
29-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Clean up the virtual GRF handling.
Now, virtual GRFs are consecutive integers, rather than offsetting the
next one by the size. We need the size information to still be around
for real register allocation, anyway.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 0efea25c4b9c6b5505fdbba25b525efb27468de4 |
|
30-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i956: Make new FS discard do its work in a temp, not the null reg!
Fixes:
glsl-fs-discard-02 (GPU hang)
glsl1-discard statement (2)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 1747aa6755088398108febb121a80d9572c1533e |
|
29-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for builtin uniforms to the new FS backend.
Fixes 8 piglit tests.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 9ac910cfcddf1b6e7c520261371e78fc9bcbddcf |
|
29-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Clean up obsolete FINISHME comment.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| ff0eb45f47ebf2fcc1af06a8b6b934c79dff1d41 |
|
29-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix array indexing of arrays of matrices.
The deleted code was meant to be handling indexing of a matrix, which
would have been a noop if it had been correct.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 17f3b8097d01a63917afaaefccd6eea070271652 |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't try to emit interpolation for unused varying slots.
Fixes:
glsl-fs-varying-array
glsl-texcoord-array
glsl-texcoord-array-2
glsl-vs-varying-array
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 5272c6a7a23ba74c696608fc2cb07fbfaf9e822a |
|
03-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Do interpolation for varying matrices and arrays in the FS backend.
Fixes:
glsl-array-varying-01
glsl-vs-mat-add-1
glsl-vs-mat-div-1
glsl-vs-mat-div-2
glsl-vs-mat-mul-2
glsl-vs-mat-mul-3
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| b9a59f0358f6f6afc7fafc1b417fa1b2c4cdaf37 |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for ARB_fragment_coord_conventions to the new FS backend.
Fixes:
glsl-arb-frag-coord-conventions
glsl-fs-fragcoord
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 701c5f11c9102047c8962f053843469ada3b3a1a |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for ir_loop counters to the new FS backend.
Fixes:
glsl1-discard statement in for loop
glsl-fs-loop-two-counter-02
glsl-fs-loop-two-counter-04
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 89f6783d1769c61b835b49a5fb4405a3249031f4 |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for MRT to the new FS backend.
Fixes these tests using gl_FragData or just gl_FragDepth:
glsl1-Preprocessor test (extension test 1)
glsl1-Preprocessor test (extension test 2)
glsl-bug-22603
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 86fd11262cb5697e5c3563e876781b3587788737 |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for non-color render target write data to new FS backend.
This is the first time these payload bits have made sense to me,
outside of brw_wm_pass* structure.
Fixes: glsl1-gl_FragDepth writing
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 2999a44968a045b5516ff23d70b711b01bd696a5 |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set up sampler numbers in the FS backend.
+10 piglits
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 9e96c737f8cb6faebf7c7339cfcf14f80ed8e73c |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Subtract instead of adding when computing y delta in new FS backend.
Fixes 7 piglit cases.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 5f7bd68149e59b6940e891928faa532bce0271f6 |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gl_FrontFacing to the new FS backend.
Fixes:
glsl1-gl_FrontFacing var (1)
glsl1-gl_FrontFacing var (2)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 6bf12c8b7366a9db8c88b9cacaa06266b41a73b5 |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for struct, array, and matrix uniforms to FS backend.
Fixes 16 piglit cases.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| ba481f2046e6427c8bd7fc5f8cb8ef3059a7881a |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for dereferencing structs to the new FS backend.
Fixes: glsl1-struct(2)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 07fc8eed8f0398063d87acf3a7ee392da4184822 |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set the variable type when dereferencing an array.
We don't set the type on the array virtual reg as a whole, so here's
the right place.
Fixes:
glsl1-GLSL 1.20 arrays
glsl1-temp array with constant indexing, fragment shader
glsl1-temp array with swizzled variable indexing
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 719f84d9aba6b016e1069e0461cbfc4211f5a3b5 |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up the FS backend for the variable array indexing pass.
We need to re-run channel expressions afterwards as it generates new
vector expressions, and we need to successfully support conditional
assignment (brw_CMP takes 2 operands, not 1).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 57edd7c5c116926325e3a86cef618bfd1b5881c1 |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix valgrind complaint about base_ir for new FS debugging.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 1723fdb3f0004a685351d005ba0f5bfc1c2a852e |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Apply the same set of lowering passes to new FS as to Mesa IR.
While much of this we will want to support natively, this should make
the task of reaching the Mesa IR backend's quality easier.
Fixes:
glsl-fs-main-return.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| e10508812aed4c41c62ea27ac540c8d079bece07 |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Actually track the "if" depth in loop in the new FS backend.
Fixes:
glsl-fs-if-nested-loop.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| fceb78e3cc67d035a69613826f46a18e62235f5c |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix negation in the new FS backend.
Fixes:
glsl1-Negation
glsl1-Negation2
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 94d44c33c0ced34e222517ed9c3b72d3c5e3b9f0 |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for dFdx()/dFdy() to the FS backend.
Fixes:
glsl-fwidth
glsl-derivs-swizzle
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 169ff0cc9d189f5a00a2a94313a6ce1503d1d5b9 |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Handle all_equal/any_nequal in the new FS.
These are generated for scalar operands instead of plain equal/nequal.
But for scalars, they're the same anyway. +30 piglits.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 11ba8bafdbb31f40ecbb6478e26496b547d34c68 |
|
27-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up writemasked assignments in the new FS.
Not sure how I managed to get tests to succeed without this. +54 piglits.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 03923ff95ed2c1ee54f0132e87e277b6cf07b7f5 |
|
22-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Warning fix for vector result any_nequal/all_equal change.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 6ef5f212343c0557c4fca272d8236226c1a7c87a |
|
10-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add switch cases for ir_unop_noise, which should have been lowered.
Fixes compiler warnings.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| e591c4625cae63660c5000fbab366e40fe154ab0 |
|
05-Sep-2010 |
Luca Barbieri <luca@luca-barbieri.com> |
glsl: add several EmitNo* options, and MaxUnrollIterations
This increases the chance that GLSL programs will actually work.
Note that continues and returns are not yet lowered, so linking
will just fail if not supported.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 32b84ef4ca50998914184fc4600d8e43674a9a22 |
|
05-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Make pixel_xy results UW.
There is a restriction on the destination of an operation involving a
vector immediate being 128-bit aligned and the destination horizontal
stride being equivalent to 2 bytes. Fixes bad pixel_x results from
gl_FragCoord, where each pair had the same value.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 5afdfa222fa9ec8c54e7d6957d2680c37a9eb715 |
|
06-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't bother with RNDZ for f2i.
The default type conversion for MOV should be fine, and RNDZ actually
requires two instructions.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 3fb5377ba57aea356a81c521c0cf1975dc290b61 |
|
04-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Align the start of attribute interp coefficients in FS to use PLN.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 3dbc9ea0a35653a0484d3b0a65a305626c251789 |
|
03-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Just assert when we flagged a compile error in the FS for now.
Dumping back to potentially 16-wide dispatch doesn't really work out
at the moment, and hopefully I'll just be able to resolve all the
failures so we never have to do this at all.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 42fc60cadcea920e9d67581de133a47effcc8441 |
|
03-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Clean up fs_reg setup by using a helper for constructors.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 1fcb5a9858b7513c5130006933edc224b69be82d |
|
29-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for loops to the new FS backend.
This includes a handy little safety check to prevent the loop from
going "too long", as permitted by the spec. I haven't gone out of my
way to test it, though…
Fixes 20 more piglit tests.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| b0a933a4d91c47e697459921073f8afe668bac31 |
|
29-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add "discard" support to the new FS backend.
Fixes 3 testcases related to discard.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4ff25c2106fb981334bdc1b032fcf37d8753ba62 |
|
29-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix the new implementation of ir_unop_sign to match brw_wm_emit.c
Like the comparison operations, this suffered from CMP only setting
the low bit. Doing the AND instructions would be the same instruction
count as the more obvious conditional moves, so do cond moves.
Fixes glsl-fs-sign and 6 other cases, like trig functions that use
sign() internally.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 40aadafa91ef5b931436d400fedafd720d59deff |
|
29-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for texturing with bias to i965 FS backend.
Fixes 5 piglit tests for bias. Note that LOD is a 1.30 feature and
not yet supported.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 735af3959f4a4eb5940835c5a4117a020f103414 |
|
28-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add initial support for texturing to the new FS backend.
Fixes 11 piglit tests.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 3d4597f9d4c93d285825d5a6505d4ee7ce6e2c3e |
|
29-Aug-2010 |
Cedric Vivier <cedricv@neonux.com> |
i965: Move libdrm/C++ hack introduced in fa2deb3d to intel_context.h
Fixes build on Linux/GCC 4.4 as libdrm includes are also used by other
brw_fs_*.cpp files.
Bug #29855
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| d20c2766182b632fba296eff7328bf14c802096e |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't strip negate/abs flags when assigning uniform locations.
Fixes glsl-algebraic-sub-zero-4.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| f0aa2d6118b1af7434b7551227cd72c588568e65 |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add missing handling for BRW_OPCODE_SEL.
Fixes 4 piglit tests about min, max, and clamp.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 38d01c5b272d28a805e7598bad2f2ef5c8da732a |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Mask out higher bits of the result of BRW_CMP producing a boolean.
When it says it sets the LSB, that's not just a hint as to where the
result goes. Only the LSB is modified. Fixes 20 piglit cases.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 4229a93cc756b3ade02dcf93d806610f95497ad3 |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix the types of immediate integer values.
When we're trying to do integer ops, handing a float in doesn't help.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 41e75cde2605e62ab691fd725a8a7259f40f5122 |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add translation for RNDD and RNDZ.
Fixes:
glsl-fs-any.
glsl1-integer division with uniform var
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 31c9f468f35637ce3b82e59a43c49c949d59ee9e |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for ir_binop_mod using do_mod_to_fract.
Fixes glsl-fs-mod.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 53290900db2f13fd9ab56b8f9780fa309d31780f |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix swapped instructions in ir_unop_abs and ir_unop_neg.
Fixes glsl-fs-neg and 5 other tests.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 2776ad2641469d3bdb6f53b99fbd748efd277c51 |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add generate() handling for AND, OR, XOR.
10 more piglit tests pass.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 130368f910a806a12287c7561df7dddd0fc8be40 |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for if instructions in the new FS backend.
20 more piglit tests pass.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a0ffee2cd79deb5a437784e25de6512d7f8e6bb8 |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: When encountering an unknown opcode in new FS backend, print its name.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 40932c1752b0fa918d764e3367f5ab450033304a |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix the maximum grf counting in the new FS backend.
glsl-algebraic-rcp-rsq managed to use 33 registers, and we claimed to
only use 32, so the write to g32 would go stomping over the precious
g0 of some other thread.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 166b3fa29d4b5af8d4e8c410ed71e4348b65bbd9 |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Validate the IR tree after doing our custom optimization passes.
This wouldn't catch the last failure fixed in them, because we don't
validate assignments well (due to the fact that we've got a pretty
glaring inconsistency in how we handle assignment writemasking), but
it could catch other failure we may produce.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 55ced3367543994bd21b48326c64edb743001145 |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add a bit of support for matrices to the new FS.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 91a037b5e1374fe0574480a579bd36c71b75f9c2 |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix destination writemasking in the new FS.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a4d97d3726046fca66f3dbcfbe7b276c5eb80b3b |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add preliminary support for uniforms to the new FS backend.
+269 piglits
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 3dff682b6595c8771655307ed00bd8844f22238c |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Abort on gl_FragDepth in the new FS backend for now.
It hangs the GPU due to FB_WRITE handling being incomplete. There are
bigger issues to handle first.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 1a3de23509b8170ee87223dc63e992e195a04de5 |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up and actually enable the NewShader and NewShaderProgram hooks.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| fa2deb3ddc8dc9e3eedf7f3dc1d2d2945a95f79b |
|
27-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Hack in avoidance of c++ reserved keyword in libdrm.
I'm also fixing this upstream in libdrm, but this avoids new libdrm
dependency for the moment.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 363d0f6774b4c6b825f5b903284da1cd51a91986 |
|
26-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add GLSL IR-level source annotation and comments to new FS debug.
This should make debugging way easier, as now we have context for
reading large programs.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 7268bd82f60b1c9642a48dcfff6d77b2897222cd |
|
26-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use the implied move in brw_math() in the new FS.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| e85f8272d0757989aeab650fbf929b382d671492 |
|
17-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for in varyings to the new FS codegen.
At least some tests, like glsl-vs-sign, now work.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| dcb7c0009bf0a1e0c4fb1aae4b7b07efcc0ed173 |
|
16-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Start building the codegen visitor.
This can successfully emit a real program that generates magenta now.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 9763d0a82a1ee605a8794f199d432824fb972b6a |
|
26-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Start building direct GLSL2 IR to 965 assembly codegen.
Our channel-expressions and vector-splitting changes now happen into a
private copy of the IR that we maintain for ourselves. Uniform
assignment still happens by the core, so we continue using Mesa IR
generation not just for swrast fallbacks but also for uniform values
(since there's no storage for their contents other than
shader_program->FragmentProgram->Parameters->ParameterValues). And
most importantly, at the moment no actual codegen is hooked up other
than emitting our favorite color to the framebuffer.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| c1dfdcb93a8991788032d4906c5bf1a5b48cdc48 |
|
26-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add new pass to split vectors into scalar variables
Combined with the previous pass, this lets other optimization passes
do their work thanks to ir_tree_grafting. Still have regression in
instruction count with INTEL_NEW_FS, but register count is even
better.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| 3a8ad33dde2f059b82ebf09f5cffa66c86f2e734 |
|
13-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add a pass for the FS to reduce vector expressions down to scalar.
This is a step towards implementing a GLSL IR backend for the 965
fragment shader. Because it has downsides with the current codegen,
it is hidden under the environment variable INTEL_NEW_FS.
This results in an increase in instruction count at the moment (1444
-> 1752 for glsl-fs-raytrace, 345 -> 359 on my demo), because dot
products are turned into a series of multiplies and adds instead of a
custom expansion of MULs and MACs, and by not splitting the variable
types up we don't get tree grafting and thus there are extra moves of
temporary storage. However, register count drops for the non-GLSL
path (64 -> 56 on my demo shader) because the register allocator sees
all the sub-operations.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|
| a1bebf73dfdaf2cd23286aa74271b87166589901 |
|
11-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Start building 965 FS backend.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs.cpp
|