| a6411520b40d59a8806289c7aaea4a6b26a54443 |
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06-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/fs: Rename virtual_grf_next to virtual_grf_count.
"count" is a more useful name, since most of the time we're using it for
looping over the variables.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
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| 3f929efa2872aa5a4402520ec9fd551392e2413a |
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18-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend.
In order to compute centroid varyings correctly, the fragment shader
needs to be able to load the current pixel/sample mask into a flag
register. This patch adds an opcode to the fragment shader back-end
to do this; the opcode gets translated into the instruction
mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all }
Since this instruction clobbers f0, instruction scheduling has to
treat it the same as instructions that have a conditional modifier.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
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| ff8f272b0d02b41a0ce34ab6af7119b9e06f4961 |
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29-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Implement integer quotient and remainder math operations.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
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| 2f0edc60f4bd2ae5999a6afa656e3bb3f181bf0f |
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26-Aug-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Fix Android build by removing relative includes
Replace each occurence of
#include "../glsl/*.h"
with
#include "glsl/*.h"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
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| 65b5cbbcf783f6c668ab5b31a0734680dd396794 |
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05-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965: Rename math FS_OPCODE_* to SHADER_OPCODE_*.
I want to just use the same enums in the VS.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
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| 6034b9a5124475d300d0678bd2fb6160865fa972 |
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03-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Create a shared enum for hardware and compiler-internal opcodes.
This should make gdbing more pleasant, and it might be used in sharing
part of the codegen between the VS and FS backends.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
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| c9e81fe14f36933617c862efb15ae09194485eab |
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15-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop the reg/hw_reg distinction.
"reg" was set in only one case, virtual GRFs pre register allocation,
and would be unset and have hw_reg set after allocation. Since we
never bothered with looking at virtual GRF number after allocation
anyway, just use the same storage and avoid confusion.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
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| 44ffb4ae207e48f78fae55925601b8708ed09c1d |
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29-Jul-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Stop using the exec_list iterator.
The old style has gone out of favor in the project, but I kept copy
and pasting from existing iterator code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
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| 615117ce4efd041459f7d4b0c77aa8e248345e66 |
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23-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Track fixed GRF regs separate from allocated GRF file in scheduling.
There's an assumption here that fixed GRFs will never intersect with
the allocated GRFs. That's true today, though it might change some
day if we decide to register-allocate the regs containing push
constants once they're dead.
This fixes a regression in 0f7325b89038937bd428f7c89ed9859189a0ab0b in
Lightsmark from the texture instructions now containing g0 references
instead of having that be implied. Performance is improved 15.2% +/-
3.6% (n=3).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34968
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
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| 40540cc517480720e509a63f213ab33d66409bf8 |
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20-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add a helper function for add_dep(before, after, before->latency).
This lets us avoid a bunch of before==NULL checks in the callers.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
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| 91d1a141589441b203a2270417ae665f0616ea3c |
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23-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Fix and enable the instruction scheduler for 16-wide.
Most of the work of the scheduler is agnostic to wide dispatch. It
operates on our virtual GRF file, which means instructions are
generally referring to 8 or 16 wide naturally. For the MRF file
management we're trying to track the actual hardware MRF file, so we
need to watch if an instruction writes multiple MRFs.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
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| af20328271425c217630b5114ee172bd8387a91a |
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23-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Disable some optimization passes under 16-wide for now.
These are fixable for 16, but that can wait until after it's basically
working.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
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| d3073f58c17d8675a2ecdd5dfa83e5520c78e1a8 |
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21-Jan-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
Convert everything from the talloc API to the ralloc API.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
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| e256e4743c3f8f924f0d191759d9428f33f3e329 |
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19-Jan-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
glsl, i965: Remove unnecessary talloc includes.
These are already picked up by ir.h or glsl_types.h.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
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| b41d323c90da47d720c015a18aa90e9efbb689aa |
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19-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Take the shared mathbox into account in instruction scheduling.
I don't have evidence for this amounting to any improvement,
but it does codify a bit more what we understand so far about
the pipeline.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
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| 63879d90ace519749fed228ca0e21b5b56c7e1c0 |
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19-Jan-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add an instruction scheduler.
Improves performance of my GLSL demo by 5.1% (+/- 1.4%, n=7). It also
reschedules the giant multiply tree at the end of
glsl-fs-convolution-1 so that we end up not spilling registers,
producing the expected level of performance.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
|