| 4433b0302d0aa9dc61002e8bb4fd1b752b0be338 |
|
20-Apr-2012 |
Brian Paul <brianp@vmware.com> |
intel: use _mesa_is_winsys/user_fbo() helpers
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 62ca17101c8282732d5c05e7891c3380a0701e4f |
|
09-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add missing _NEW_PROGRAM dirty bit to the brw_sf_state atom.
Also, annotate the use of _NEW_POINT as long as we're adding a comment.
NOTE: This is a candidate for the 7.11 branch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| c4aaf85285fc9484e95e9cda89db9cc6923259f4 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Move unit state setup to emit() time.
It is only needed in time for brw_psp_urb_cbs(), which is also an emit().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 47f1d9deffee8aeb2d73d8e06f829d32125f944c |
|
24-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove "single threaded" INTEL_DEBUG mode.
According to the docs for 3DSTATE_PS (Gen7+) and 3DSTATE_WM (Gen6),
there is a platform dependent value for the minimum number of pixel
shader threads. It may also vary based on whether WIZ Hashing is on.
For example, Ivybridge requires at least 4 threads if WIZ hashing is
disabled, and 8 if it's enabled. Programming it to use less threads is
illegal. Sandybridge appears to have similar restrictions.
So on newer platforms, INTEL_DEBUG=sing will probably just hang the GPU.
Rather than try to patch it up for newer platforms and extend it to
support geometry shaders, just remove it as it isn't that useful anyway.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 39fc725b0c81db8d76cb490488cd95de5c4d7a79 |
|
23-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: SF: Move the computation of urb_entry_read_offset.
This patch moves the computation of the SF URB entry read offset from
upload_sf_unit() to its own function, so that it can be re-used when
creating the gen4-5 SF program.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| d375df220fae47f38944c4832bcbd5f5d568884c |
|
23-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add a type argument to brw_state_batch().
I want to make brw_state_dump.c handle more than just the last
statechange, so I want to keep track of what's in the batch state. By
using AUB file numbering for most of these packets, this may be
reusable for aub dumping.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| c173541d9769d41a85cc899bc49699a3587df4bf |
|
27-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use state streaming on programs, and state base address on gen5+.
There will be a little bit of thrashing of the program cache BO as the
cache warms up, but once the application is in steady state, this
reduces relocations on gen5 and later.
On my T420 laptop, cairogl firefox-talos-gfx performance improves 2.6%
+/- 1.3% (n=6). No statistically significant performance difference
on nexuiz (n=5).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 855f56ca13c1003396a81da1a110357d624a2101 |
|
25-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Move scissor state to state streaming.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 8d2047ca7e8a533e1853a2ba51cd1bd6e52ae4a3 |
|
22-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Move the SF VP to state streaming.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 88022278f71ed3ea9613a7fa72a03367f75443d3 |
|
09-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move the SF VP from state caching to state streaming.
This is a 49.6% +/- 2.0% (n=9, IPS outlier removed) performance
improvement for the hacked-up-for-cache-misses scissor-many, and no
statistically significant performance difference for the
hacked-up-for-cache-hits version (n=9, IPS outlier removed). No
statistically significant performance difference from ETQW (n=5) from
these last two commits.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| b1be5bd205d3efcaf4012d2c9a12831da57fc7fb |
|
09-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965: Change the SF unit from state caching to state streaming.
This is a 28.1% +/- 1.4% (n=10) performance improvement for the
hacked-up-for-cache-misses scissor-many (n=10), and no statistically
significant wall-time performance difference for the
hacked-up-for-cache-hits version (n=9, first outlier in each removed
since IPS was warming up. User time increased by about 4.7%, but
kernel time decreased equivalently).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| aaf188e3bbe29826f0fea8944243a416946e7343 |
|
09-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965: Turn SF unit and viewport structs into pointers to prep for streaming.
I wanted to separate this mechanical change from the actual work.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 63ba1ec3c1192a1b7299e5768e7721638cd5fa0b |
|
22-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Respect VS/VP point size result when enabled.
Fixes glsl-vs-point-size.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 8ad3fdc9678866b40f3d9faaaf7c6333d388907f |
|
10-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: GC the last two arguments to brw_cache_data.
Now that the binding table is streamed indirect state, they were
always NULL/0.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| df3c1a563f3d76b07ab82c7b230b0030452f36ff |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Convert remaining dri_bo_emit_reloc to drm_intel_bo_emit_reloc.
The new API makes so much more sense, I'd like to forget how the old
one worked.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 34474fa4119378ef9fbb9fb557cc19c0a1ca1f7e |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.
The slightly less mechanical change of converting the emit_reloc calls
will follow.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 64516430be1cbe4904613903887a8178f4b4fc60 |
|
20-Apr-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix scissoring when width or height is 0.
We would run into trouble due to the hardware using inclusive numbers
and the subtraction to handle that producing negative (meaning large
positive) coordinates.
Bug #27643.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| cdcef6cbf4dd80047819e9098e34a3b98bd502a4 |
|
19-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
intel: Clean up chipset name and gen num for Ironlake
Rename old IGDNG to Ironlake, and set 'gen' number for
Ironlake as 5, so tracking the features with generation num
instead of special is_ironlake flag.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 41f4d82ba8e2497d9fe27f55cb1b8707862fed46 |
|
27-Jan-2010 |
Eric Anholt <eric@anholt.net> |
intel: Clean up stale comments about cliprects.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 9b22427911ad27efc1f36faee9462c6082d0417c |
|
25-Jan-2010 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch'
Conflicts:
src/mesa/drivers/dri/intel/intel_screen.c
src/mesa/drivers/dri/intel/intel_swapbuffers.c
src/mesa/drivers/dri/r300/r300_emit.c
src/mesa/drivers/dri/r300/r300_ioctl.c
src/mesa/drivers/dri/r300/r300_tex.c
src/mesa/drivers/dri/r300/r300_texstate.c
|
| 634ec5c2abf05a9a8c27d9199ded5d1ad91e538a |
|
23-Jan-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 62a96f74c9a1fd07301d349e4181a7212fc7d45c |
|
18-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Allow for variable-sized auxdata in the state cache.
Everything has been constant-sized until now, but constant buffer
handling changes will make us want some additional variable sized
array.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 1c96e85c9d6b8c636b0636f3320d1057ab5357b3 |
|
16-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.
Saves ~480 bytes of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 3d36d6b4cf735e93a6ae5eadf28e671252fb5303 |
|
13-Nov-2009 |
Eric Anholt <eric@anholt.net> |
Merge remote branch 'origin/mesa_7_6_branch'
|
| ab12e764ba3f57ad9f0d7252262cfc6e07839928 |
|
12-Nov-2009 |
Roland Scheidegger <sroland@vmware.com> |
i965: fix EXT_provoking_vertex support
This didn't work for quad/quadstrips at all, and for all other primitive types
it only worked when they were unclipped.
Fix up the former in gs stage (could probably do without these changes and
instead set QuadsFollowProvokingVertexConvention to false), and the rest in
clip stage.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 8395da2e8af40367714c70afe299568272f36cc8 |
|
05-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Always pass the size argument to brw_cache_data.
This keeps the individual state files from having to export their
structures for brw_state_cache initialization.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 12c6973c6e32e5ee29242cb037830c1ca081f479 |
|
08-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add a note justifying domain choice for the SF VP.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| de80eeea0eebf00ee678b1a0fbd5fe67b00a8636 |
|
04-Aug-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add support for EXT_provoking_vertex.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 99174e7630676307f618c252755a20ba61ad9158 |
|
17-Jul-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 3a521d84ecc646fcc65fa3fe7c5f1fdbdebe8bc2 |
|
21-May-2009 |
Eric Anholt <eric@anholt.net> |
i956: Make state dependency of SF on drawbuffer bounds match Mesa's.
Noticed while debugging a weird 1D FBO testcase that left its existing
viewport and projection matrix in place when switching drawbuffers. Didn't
fix the testcase, though.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| ff71587b27beaf288d535e14c75e58425d7efc7a |
|
23-Apr-2009 |
Roland Scheidegger <sroland@vmware.com> |
i965: fix point size issue
need to clamp point size to user set min/max values, even for constant
point size. Fixes glean pointAtten test.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| cc8afbd3862fedfe42e51c3774960d1c7078ec53 |
|
24-Mar-2009 |
Robert Ellison <papillo@vmware.com> |
i965: fix point rasterization when rendering to FBO
The FBO pixel coordinate system, with (0,0) as the
upper-left pixel, is inverted in Y compared to the
normal OpenGL pixel coordinate system, which has
(0,0) as its lower-left pixel.
Viewport and polygon stipple are sensitive to this
inversion; so is point rasterization. The basic
fix is simple: when rendering to an FBO, instead
of the normal RASTRULE_UPPER_RIGHT that's
appropriate for OpenGL windows, use the Y inversion
RASTRULE_LOWER_RIGHT.
Unfortunately, current Intel documentation has this
value listed as "Reserved, but not seen as useful".
It does work on at least some i965-class devices,
though; and the worst that could happen if an
older device didn't support it would be incorrect
point rasterization to FBOs, which is what happens
already, so this fix is at least no worse than what
happens presently, and is better for some (and possibly
all) i965-class devices.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 3b946cde45f214be08edfbb716034d407a13c6b4 |
|
13-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: move declaration before code
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 052c1d66a1ab1f2665870dc77dab28d20416cdf1 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove brw->attribs now that we can just always look in the GLcontext.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 14321fcfde9e30d0b9f15aab3c9a057271ae6295 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Delete old metaops code now that there are no remaining consumers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| d3aa16d92f1eb228daaa49810e113d2aed06aefd |
|
29-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: use bitfields in brw_sf_unit_key struct
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| ba367f68ccacf255f78ac0c8dd066e64bbb1e5c2 |
|
29-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix render to FBO/texture orientation bugs
Anytime we're not rendering to the default/window FBO, need to invert
rendering, not just when rendering to a texture. Otherwise, if a FBO
consists of a mix of textures and renderbuffers the up/down orientation
was inconsistant.
Fixes shadowtex.c bad rendering.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 3b23a8e07d59ff6ee766e7d3eb384137279a5250 |
|
26-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: scissor rect was inverted when rendering to texture
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| a61a1a8181f05e07de1c0bccad109f4ad529a298 |
|
16-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix polygon culling bug when rendering to a texture/FBO
Since we use an inverted viewport transformation for render to texture, that
inverts front/back polygon orientation.
Now glCullFace(GL_FRONT / GL_BACK) works correctly.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 356428d4e4dba433b405f63ff918d76eaf4b4215 |
|
14-Sep-2008 |
Matthieu Herrb <matthieu.herrb@laas.fr> |
replace nearbyint() by rint() for now.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 9dadfc09a9dd492f14eec8de060d3f5198c766ec |
|
03-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Fix up SF max_threads.
We were dividing the number of URB entries by two to get number of threads,
which looks suspiciously like a copy'n'paste-o from brw_vs_state.c. Also, the
maximum number of threads is 24, not 12.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 3628185f566e178a12b493fb89abf52b4b281f99 |
|
06-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| d2796939f18815935c8fe1effb01fa9765d6c7d8 |
|
08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Update to new check_aperture API for classic mode.
To do this, I had to clean up some of 965 state upload stuff. We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 407ce3da3c53c9ebba0fbf827d7b0f610122d44b |
|
11-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel-gem] Chase domain flag renaming in the DRM.
This is an API breakage only.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| 4b5b008d54e86ac4f0a2176429d062100978ca8c |
|
03-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert drivers to using libdrm bufmgr code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|
| ab50ddaa9173ae108833db0edb209045788efc41 |
|
07-May-2008 |
Eric Anholt <eric@anholt.net> |
GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.
The GEM flags are much more descriptive for what we need. Since this makes
bufmgr_fake rather device-specific, move it to the intel common directory.
We've wanted to do device-specific stuff to it before.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
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| 008653ac55776d6b1c6d1627ad20937aa1c4dbda |
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17-Apr-2008 |
Dave Airlie <airlied@redhat.com> |
i965: initial attempt at fixing the aperture overflow
Makes state emission into a 2 phase, prepare sets things up and accounts
the size of all referenced buffer objects. The emit stage then actually
does the batchbuffer touching for emitting the objects.
There is an assert in dri_emit_reloc if a reloc occurs for a buffer
that hasn't been accounted yet.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
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| 8d5231a3582e4f2769ac0685cf0174e09750700e |
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17-Mar-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] round pointsize to nearest int according to spec
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
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| 8e444fb9e2685e3eac42beb848b08e91dc20c88a |
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29-Jan-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: new integrated graphics chipset support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
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| ff73c783cc47361ff0dd819c82d067b4b85870dd |
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06-Jan-2008 |
Brian <brian.paul@tungstengraphics.com> |
Simplify ctx->_NumColorDrawBuffers, _ColorDrawBuffers and fix bug 13835.
These fields are no longer indexed by shader output. Now, we just have
a simple array of renderbuffer pointers.
If the shader writes to gl_FragData[i], send those colors to the N
_ColorDrawBuffers. Otherwise, replicate the single gl_FragColor (or
the fixed-function color) to the N _ColorDrawBuffers.
A few more changes and simplifications can follow from this...
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
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| 8abffada70fcd62e3c2dcbcdc6d00d258805326b |
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03-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert relocations to not be cleared out on buffer submit.
We have two consumers of relocations. One is static state buffers, which
want the same relocation every time. The other is the batchbuffer, which gets
thrown out immediately after submit. This lets us reduce repeated computation
for static state buffers, and clean up the code by moving relocations nearer
to where the state buffer is computed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
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| 77e6cf8c1758c6b3091adf95ead96fbe9a996a17 |
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02-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Convert SF unit to use a cache key instead of brw_cache_data.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
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| bea6b5fe5aa3138cec8d057766ae48da4aa57dee |
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20-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Enable EXT_framebuffer_object.
To do so, merge the remainnig necessary code from the buffers, blit, span, and
screen code to shared, and replace it with those.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
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| 447facfcd6d807128ebf6ba3efc894180b447494 |
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17-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Simplify scissor handling by using DrawBuffer values.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
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| 2c9e515d8607fb91f08c500a841cdf7f32bda346 |
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17-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace our own depth constants in intel context with GL context ones.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
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| 38bad7677e57d629eeffd4ef39a7fc254db12735 |
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14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace the state cache suballocator with direct dri_bufmgr use.
The user-space suballocator that was used avoided relocation computations by
using the general and surface state base registers and allocating those types
of buffers out of pools built on top of single buffer objects. It also
avoided calls into the buffer manager for these small state allocations, since
only one buffer object was being used.
However, the buffer allocation cost appears to be low, and with relocation
caching, computing relocations for buffers is essentially free. Additionally,
implementing the suballocator required a don't-fence-subdata flag to disable
waiting on buffer maps so that writing new data didn't block on rendering using
old data, and careful handling when mapping to update old data (which we need
to do for unavoidable relocations with FBOs). More importantly, when the
suballocator filled, it had no replacement algorithm and just threw out all
of the contents and forced them to be recomputed, which is a significant cost.
This is the first step, which just changes the buffer type, but doesn't yet
improve the hash table to not result in full recompute on overflow. Because
the buffers are all allocated out of the general buffer allocator, we can
no longer use the general/surface state bases to avoid relocations, and they
are set to 0 instead.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
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| 77e0523fb7769df4bf43747e136b1653b2421b97 |
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04-Oct-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace various alignment code with a shared ALIGN() macro.
In the process, fix some alignment issues:
- Scratch space allocation was aligned into units of 1KB, while the allocation
wanted units of bytes, so we never allocated enough space for scratch.
- GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of
ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
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| 505453a04e8ba5e394c34401bd9ec320ffce2423 |
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02-Aug-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
fix fd.o bug #11804
glPolygonMode with point sprite on i965
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
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| a6dad044e24358af9fe5764ca7b342f4ed4804db |
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01-Aug-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
fix fd.o bug #11788, max point size
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
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| af2aa8e9cf88a9ee3ec338eddc9a47bf2f142cb7 |
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21-Jul-2007 |
Brian <brian.paul@tungstengraphics.com> |
Remove ctx->Point._Size and ctx->Line._Width.
The clamping for these values depends on whether we're drawing AA or non-AA
points, lines. Defer clamping until drawing time. Drivers could compute and
keep clamped AA and clamped non-AA values if desired.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
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| 9f344b3e7d6e23674dd4747faec253f103563b36 |
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09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_sf_state.c
|