| b0d23b66cf2514949650bdfa9c918ab2fb1d8986 |
|
27-Aug-2012 |
Eric Anholt <eric@anholt.net> |
intel: Move RenderMode fallback func to i915 driver.
The Fallback field of the context struct doesn't work that way on i965, and
it's the only caller of FALLBACK() in the driver.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 28fab4295e9631ca91c5ebdf26d1bee23011d57e |
|
15-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Un-hardcode WM binding table from update_texture_surface.
Currently, we mirror the VS and WM binding tables' texture entries.
That may not continue to be true, so in preparation, pass in the binding
table and surface index as arguments.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 38b748ce29a6415558bbe4886589134e3db047c8 |
|
09-Aug-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Refactor intel_downsample_for_dri2_flush
Move it from intel_screen.c to intel_context.c. Redeclare as non-static.
A future commit will use it in multiple files.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| d72ff03e699e78381049e29d89163519e6730dd4 |
|
12-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add INTEL_DEBUG=perf for failure to compile 16-wide shaders.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 79198063b8adb23536b291081f8df8571926950e |
|
12-Jul-2012 |
Eric Anholt <eric@anholt.net> |
intel: Rename INTEL_DEBUG=fall to INTEL_DEBUG=perf.
I want to introduce some more debug output for performance surprises that
includes fallbacks, but aren't necessarily software rasterization. Leave
INTEL_DEBUG=fall in place for those that have used that flag before.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 5bffbd7ba2ba2ff21469b2a69a0ed67f0802fec7 |
|
20-Jun-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add an offset argument to constant buffer setup.
We'll use this for UBO surfaces.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 860d5bdf984730f69cd19b4f7145f3c84b57d33d |
|
12-Jun-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add hardware context support.
With fixes and updates from Ben Widawsky and comments from Paul Berry.
v2: Use drm_intel_gem_context_destroy to destroy hardware context;
remove useless initialization of hw_ctx, both suggested by Eric.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 54308f78a2f8675bfd854761f9cd8a6b71e119d0 |
|
21-May-2012 |
Eric Anholt <eric@anholt.net> |
i965: Drop a layer of indirection in doing HiZ resolves.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| ea8e854b2cefc3f3590b6c19e6108a471be951ba |
|
07-May-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Completely annotate the batch bo when aub dumping.
Previously, when the environment variable INTEL_DEBUG=aub was set,
mesa would simply instruct DRM to start dumping data to an .aub file,
but we would not provide DRM with any information about the format of
the data in various buffers. As a result, a lot of the data in the
generate .aub file would be unannotated, making further data analysis
difficult.
This patch causes the entire contents of each batch buffer to be
annotated using the data in brw->state_batch_list (which was
previously used only to annotate the output of INTEL_DEBUG=bat). This
includes data that was allocated by brw_state_batch, such as binding
tables, surface and sampler states, depth/stencil state, and so on.
The new annotation mechanism requires DRM version 2.4.34.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| f28a7d0e77ffbeb2a27bda132d4334b3649be3a2 |
|
30-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
intel: Work around differences between C and C++ scoping rules.
In C++, if a struct is defined inside another struct, or its name is
first seen inside a struct or function, the struct is nested inside
the namespace of the struct or function it appears in. In C, all
structs are visible from toplevel.
This patch explicitly moves the decalartions of intel_batchbuffer to
toplevel, so that it does not get nested inside a namespace when
header files are included from C++.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 434fc8bde41f07687ad8941ceba03c4b3e0e75bb |
|
27-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
intel: Add extern "C" declarations to headers
These declarations are necessary to allow C++ code to call C code
without causing unresolved symbols (which would make the driver fail
to load).
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 180aecb6dce1df55eae674f0f72adbc6f4d872b9 |
|
13-Aug-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add initial IS_HASWELL() macros.
For now, these all return 0, as I don't yet want to enable Haswell
support. Eventually they will be filled in with proper PCI IDs.
Also add an is_haswell field similar to is_g4x to make it easy to
distinguish Gen7 and Gen7.5.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 0247d89183e26fbd07e4176ff6f8d1b4989e24ab |
|
07-Mar-2012 |
Eric Anholt <eric@anholt.net> |
intel: Ask libdrm to dump an AUB file if INTEL_DEBUG=aub.
It also asks for BMPs in the aub file at SwapBuffers time.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 67d3ff760a33f3f98b89d3a6422bb85c199a9963 |
|
06-Mar-2012 |
Eric Anholt <eric@anholt.net> |
intel: Drop the INTEL_STRICT_CONFORMANCE environment variable.
If you want to test the graphics driver, you want to test it under the
conditions that users will see, not some set of additional fallbacks.
If you want to test swrast, run the swrast driver (or no_rast=true)
instead.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| f172eae8b23d0612865895c52af745021ae20a4c |
|
02-Mar-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
i965: fixup W-tile offset computation to take swizzling into account
There's even a comment in the code containing the right swizzling
computations!
Previously this has not been noticed because we need to manually
enabled swizzling on snb/ivb (kernel 3.4 will do that) and we
don't use the separate stencil on ilk (where the bios enables
swizzling). This fixes
piglit ./bin/fbo-stencil readpixels GL_DEPTH32F_STENCIL8 -auto
on recent drm-intel-next kernels.
Also remove the comment about ivb, it's stale now.
Swizzling detection is done by allocating a temporary x-tiled
buffer object. Unfortunately kernels before v3.2 lie on snb/ivb
because they claim that swizzling is enable, but it isn't. The
kernel commit that fixes this for backport to pre-v3.2 is
commit acc83eb5a1e0ae7dbbf89ca2a1a943ade224bb84
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Mon Sep 12 20:49:16 2011 +0200
drm/i915: fix swizzling on gen6+
But if the kernel doesn't lie, this now works on swizzling and
not swizzling machines.
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 7def293204977c41ea35198af147f743a31b1889 |
|
01-Feb-2012 |
Eugeni Dodonov <eugeni.dodonov@intel.com> |
intel: verify if hardware has LLC support
Rely on libdrm HAS_LLC parameter to verify if hardware supports it. In
case the libdrm version does not supports this check, fallback to older
way of detecting it which assumed that GPUs newer than GEN6 have it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 796f44d77906342e5912e7da6bdba1ba86bab9f0 |
|
20-Jan-2012 |
Eric Anholt <eric@anholt.net> |
intel: Pass the gl_renderbuffer to render_target_supported() vtable method.
I'm going to want to go looking at it for an integer texture fix.
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| ccf0d31a210baf062dcc0e0c19527cdbbade0ac9 |
|
12-Jan-2012 |
Eric Anholt <eric@anholt.net> |
intel: Fix warnings of undefined ffs().
For some reason these started showing up with the automake conversion.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| c4089d444a1736dba0c3d9c389ac216ce8711da8 |
|
30-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen7: Use the updated interface for SO write pointer resetting.
The new kernel patch I submitted makes the interface opt-in, so all
batchbuffers aren't preceded by the 4 MI_LOAD_REGISTER_IMMs. This
requires the updated i915_drm.h present in libdrm 2.4.30.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| b890f1090c6d640605d5c45cfcf71cef91d59865 |
|
16-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Make the batchbuffer flush debug more useful.
We were printing out the line triggering the flush, but a variety of
different causes just printed the line number for intel_flush()'s call
of intel_batchbuffer_flush(). Plumb the line numbers from the caller
of intel_flush() on through.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| d84a180417d1eabd680554970f1eaaa93abcd41e |
|
17-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Base HW depth format setup based on MESA_FORMAT, not bpp.
This will make handling new formats (like actually exposing Z32F)
easier and more reliable.
v2: Remove the check for hiz buffer -- the MESA_FORMAT should really
be giving us the value we want even for hiz.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 27505a105a4bf8b7329b87d29e1625e545508e4e |
|
16-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i915: Move the texture format setup for this driver out of shared code.
The i965 driver is now enabling all of these formats on its own from
the surface format table.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 6661b7596f3b26a773ccde79f018179713b6b6e0 |
|
15-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add the context to the render_target_supported() vtbl method.
We're going to want to provide different answers per chipset
generation.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| f17b12278dcc0e370d04a2a9a73677ab4c9f2c26 |
|
17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Change signature of HiZ resolve functions
Now that intel_renderbuffer::region has been replaced with a miptree, the
HiZ functions region parameter must be replaced with a miptree parameter.
Change the return type from bool to void.
Rename the 'depth' parameter to 'layer', because it will correspond to
irb->mt_layer.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 5d448b42b7143a1a38911b23d94b5c5d5bfa79f0 |
|
01-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Add new vtable entries for surface state updating functions.
Gen7+ SURFACE_STATE is different from Gen4-6, so we need separate
per-generation functions for creating and updating it. However, the
usage is the same, and callers just want to utilize the appropriate
functions with minimal pain. So, put them in the vtable.
Since these take a brw_context pointer and are only used on Gen4, just
add a forward declaration. This is the simplest (if not cleanest)
solution. It would be nicer to have a i965-specific vtable, but that's
a refactor for another day.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| ac6a376f528e4867b8422e42fd36c10e4fa79cfb |
|
19-Oct-2011 |
Eric Anholt <eric@anholt.net> |
intel: Don't force a batchbuffer flush in readpixels.
Renderbuffer mapping handles flushing the batchbuffer if required, so
all we need to do is make sure any pending rendering has reached the
batchbuffer.
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 3faf56ffbdebef04345ebb1fa8e0d50b4beeedb2 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add an interface for saving/restoring the batchbuffer state.
This will be used to avoid the prepare() step in the i965 driver's
state setup. Instead, we can just speculatively emit the primitive
into the batchbuffer, then check if the batch is too big, rollback and
flush, and replay the primitive.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 47f1d9deffee8aeb2d73d8e06f829d32125f944c |
|
24-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove "single threaded" INTEL_DEBUG mode.
According to the docs for 3DSTATE_PS (Gen7+) and 3DSTATE_WM (Gen6),
there is a platform dependent value for the minimum number of pixel
shader threads. It may also vary based on whether WIZ Hashing is on.
For example, Ivybridge requires at least 4 threads if WIZ hashing is
disabled, and 8 if it's enabled. Programming it to use less threads is
illegal. Sandybridge appears to have similar restrictions.
So on newer platforms, INTEL_DEBUG=sing will probably just hang the GPU.
Rather than try to patch it up for newer platforms and extend it to
support geometry shaders, just remove it as it isn't that useful anyway.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 7b0f748efa5af84668cc3609a0070163bfa22607 |
|
20-Sep-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Add HiZ operations to intel_context::vtbl for all drivers
Add the following to the vtbl:
hiz_resolve_depthbuffer
hiz_resolve_hizbuffer
For all drivers for which HiZ is not enabled, the methods are set to be
no-ops. If HiZ is enabled, the methods are currently to set to empty
stubs.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| e9adfa2ba1af9c3579b25327335c47118b6c7c3f |
|
06-Oct-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Assert that no batch is emitted if a region is mapped
What I would prefer to assert is that, for each region that is currently
mapped, no batch is emitted that uses that region's bo. However, it's much
easier to implement this big hammer.
Observe that this requires that the batch flush in intel_region_map() be
moved to within the map_refcount guard.
v2: Add comments (borrowed from anholt's reply) explaining why the
assertion is a good idea.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 9559ca600dde0877fe0abd04dd789bd5a3cdfbde |
|
27-Sep-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Split brw_set_prim into brw/gen6 variants
The "slight optimization to avoid the GS program" in brw_set_prim() is not
used by Gen 6, since Gen 6 doesn't use a GS program. Also, Gen 6 doesn't use
reduced primitives.
Also, document that intel_context.reduced_primitive is only used for Gen < 6
Reviewed-by: Eric Anholt <eric@anho.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 490e6470a09c3a6049e5e859d72b0b679ef5d070 |
|
24-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Introduce a new intel_context::gt field to go along with gen.
It seems that GT1/GT2 sorts of variations are here to stay, and more
special cases will likely be required in the future. Checking by PCI ID
via the IS_xxx_GTx macros is cumbersome; introducing a new 'gt' field
analogous to intel->gen will make this easier.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 3f9f1b365967a41f09431f724f43b59ca0e753b8 |
|
24-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Remove intel_context::has_xrgb_textures/has_luminance_srgb.
Seeing as they were only used once (in the same function they were
defined), having them as context members seemed rather pointless.
Remove them entirely (rather than using local variables) since the
chipset generation checks are actually just as straightforward.
While we're at it, clean up the remainder of the if-tree that set them.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| cb5e0ba2aa97df28a9faeb7ca0d2f0cdfcf4e507 |
|
13-Jul-2011 |
Eric Anholt <eric@anholt.net> |
i915: Simplify intel_wpos_* with a helper function.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| f34ec6169dc8b96e3958a42b51c9048c5f42ed80 |
|
12-Jul-2011 |
Eric Anholt <eric@anholt.net> |
intel: Move intel_draw_buffers() code into each driver.
The illusion of shared code here wasn't fooling anybody. It was
tempting to keep i830 and i915 still shared, but I think I actually
want to make them diverge shortly.
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 6e6b38860488a0b2b282866f095cea9860503a14 |
|
11-Jul-2011 |
Eric Anholt <eric@anholt.net> |
i915: Fix map/unmap mismatches from leaving INTEL_FALLBACK during TNL.
The first rendering after context create didn't know of the color
buffer yet, triggering a sw fallback. The intel_prepare_render() from
intelSpanRenderStart then found the buffer and turned off fallbacks,
but intelSpanRenderFinish was never called and things were left
mapped. By checking buffers before making the call on whether to do
the fallback pipeline or not, we avoid the fallback change inside of
the rendering pipeline.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31561
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 0ab7d6f437f2f7a1b2d84f30497f3c2013b52791 |
|
18-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Limit the workaround flush to once per primitive.
We're about to call this function in a bunch of state emits, so let's
not spam the hardware with flushes too hard.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| dfada714f8db3deea2fea3583c3c166a78db1117 |
|
18-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Use an BO instead of writing to address 0 for PIPE_CONTROL W/A.
This was spectacularly unsafe. On my system, address 0 happens to be
the hardware status page for the render ring, and the first quadword
of that happens to contain nothing we ever look at, but I sure didn't
look forward to having to debug some day when, for example, the kernel
happened to bind the ringbuffer before binding the hwsp.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 23b6f9606dc247488835745668b3686218612536 |
|
31-May-2011 |
Eric Anholt <eric@anholt.net> |
intel: Implement glFinish() correctly by waiting on all previous rendering.
Before, we were waiting for (most of) the current framebuffer to be
done, which is not quite the same thing.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| a9e65097855468529242f9076bd6ef2a6c8062c1 |
|
23-May-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Add is_hiz_depth_format() to intel_contex.vtbl
Given a format, is_hiz_depth_format() indicates if HiZ can be enabled on
a depthbuffer of that format.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 76f77cb07edf9c6a548f782c709de70aa0a41458 |
|
23-May-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Add flags to intel_context for hiz and separate stencil
Add the following flags:
intel_context.has_separate_stencil
intel_context.must_use_separate_stencil
intel_context.has_hiz
The flags are currently set to false, and will be enabled for a given
chipset once the feature is completely implemented.
Since it may be some time before these features are completed, their
values can be overridden with environment variables INTEL_HIZ and
INTEL_SEPARATE_STENCIL. Valid values for these environment variables are
"0" and "1".
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| aa3e1c25d3e4fc7e79236c717deaa838182e68c9 |
|
25-Apr-2011 |
Eric Anholt <eric@anholt.net> |
Revert "intel: use throttle ioctl for throttling"
This reverts commit 50ade6ea697953bb17e3ca7210515fbd0411cd1e.
Fixes jerky rendering again on apps that don't block on the GPU per
frame and are GPU bound (e.g. 3DMMES on Ironlake). The whole point of
this complicated throttle scheme is to wait on frame n-1 to have
started rendering before starting frame n's rendering. Otherwise, the
GPU-bound app will race ahead and call the GL to draw many
nearly-identical frames, then >0ms later get stuck waiting for them
(all dispatched at about the same time) to retire, then render a new
batch of nearly-identical frames.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 7e809f0b8d635c8d5519b3d0fdaf11ac0ddda7eb |
|
09-Apr-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Fix ROUND_DOWN_TO macro
Previously the macro would (ALIGN(value - alignment - 1, alignment)).
At the very least, this was missing parenthesis around "alignment -
1". As a result, if value was already aligned, it would be reduced by
alignment. Condisder:
x = ROUND_DOWN_TO(256, 128);
This becomes:
x = ALIGN(256 - 128 - 1, 128);
Or:
x = ALIGN(127, 128);
Which becomes:
x = 128;
This macro is currently only used in brw_state_batch
(brw_state_batch.c). It looks like the original version of this macro
would just use too much space in the batch buffer. It's possible, but
not at all clear to me from the code, that the original behavior is
actually desired.
In any case, this patch does not cause any piglit regressions on my
Ironlake system.
I also think that ALIGN_FLOOR would be a better name for this macro,
but ROUND_DOWN_TO matches rounddown in the Linux kernel.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Keith Whitwell <keithw@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 5a1fbf0f70a1c2d444f61494f86e26ca866c31d5 |
|
21-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: Fix insufficient integer width for upload buffer offset
I was being overly miserly and gave the offset of the buffer into the bo
insufficient bits, distracted by the adjacency of the buffer[4096].
Ref: https://bugs.freedesktop.org/show_bug.cgi?id=34541
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 50ade6ea697953bb17e3ca7210515fbd0411cd1e |
|
30-Dec-2010 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: use throttle ioctl for throttling
Rather than waiting on the first batch after the last swapbuffers to be
retired, call into the kernel to wait upon the retirement of any request
less than 20ms old. This has the twofold advantage of (a) not blocking
any other clients from utilizing the device whilst we wait and (b) we
attain higher throughput without overloading the system.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| aac120977d1ead319141d48d65c9bba626ec03b8 |
|
20-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Move repeat-instruction-suppression to batchbuffer core
Move the tracking of the last emitted instructions into the core
batchbuffer routines and take advantage of the shadow batch copy to
avoid extra memory allocations and copies.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 8d68a90e225d831a395ba788e425cb717eec1f9a |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: use pwrite for batch
It's faster. Not only is the memcpy more efficiently performed in the
kernel (making up for the system call overhead), but by not using mmap
we remove the greater overhead of tracking the vma of every batch.
And it means we can read back from the batch buffer without incurring
the cost of a uncached read through the GTT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 8a9e67b8df9836408270a4bc3660ec45b622ae56 |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: Buffered upload
Rather than performing lots of little writes to update the common bo
upon each update, write those into a static buffer and flush that when
full (or at the end of the batch). Doing so gives a dramatic performance
improvement over and above using mmaped access.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| e476e122207e6195a16a8c7d2cab90eeba227934 |
|
08-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: Pack dynamic draws together
Dynamic arrays have the tendency to be small and so allocating a bo for
each one is overkill and we can exploit many efficiency gains by packing
them together.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 47589c17b0ea34f2c77c8c9e633349af6d1a2f10 |
|
12-Feb-2011 |
Eric Anholt <eric@anholt.net> |
intel: Remove setup of the old dri/ meta code, which is now unused.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| a7bf7230564ac282cc957207224d16f322fa73d8 |
|
08-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add a vtbl hook for determining if a format is renderable.
By relying on just intel_span_supports_format, some formats that
aren't supported pre-gen4 were not reporting FBO incomplete. And we
also complained in stderr when it happened on i915 because draw_region
gets called before framebuffer completeness validation.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| df9f89154471ec162227ebce1681c5010f64e6e6 |
|
13-Dec-2010 |
Eric Anholt <eric@anholt.net> |
intel: Include stdbool so we can stop using GLboolean when we want to.
This requires shuffling the driconf XML macros around, since they use
true and false tokens expecting them to not get expanded to anything.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 4538ce915ba4c43290f4341ad80040b4b735eab3 |
|
11-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove INTEL_DEBUG=glsl_force now that there's no brw_wm_glsl.c
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 4ac2f09e2034d8940a0ce9426a8d5c5d74bc63bd |
|
03-Dec-2010 |
Eric Anholt <eric@anholt.net> |
intel: Add an env var override to execute for a different GPU revision.
Sometimes I'm on the train and want to just read what's generated
under INTEL_DEBUG=vs,wm for some code on another generation. Or, for
the next gen enablement we'll want to dump aub files before we have
the actual hardware. This will let us do that.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 2aa738bf26448afad5c94e6275c42b955faabfc0 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove leftover dri1 locking fields in the context.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| d3491e775fb07f891463b2185d74bbad62f3ed24 |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Rename GLvisual and __GLcontextModes to struct gl_config
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| e1aa3c234fcc30c5c07f4b896adf304414558604 |
|
30-Aug-2010 |
Cedric Vivier <cedricv@neonux.com> |
i965: Apply the rest of the old-libdrm guard patch.
Bug #29855
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| c374487a54aca2dd1053645092367c1cf0414ef7 |
|
11-Aug-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove include of texmem.h, since we haven't used it in ages.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 321014156b3f7842a84d9b9915389c9f6f6486f5 |
|
11-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for streaming indirect state rather than caching objects.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 34474fa4119378ef9fbb9fb557cc19c0a1ca1f7e |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.
The slightly less mechanical change of converting the emit_reloc calls
will follow.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| f0ff214bee64a705d3ef6610e9dc25bc1a46a460 |
|
04-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i915: Don't use XRGB8888 on 830 and 845.
The support for XRGB8888 appeared in the 855 and 865, and this format
is reserved on 830/845. This should fix a regression from
b4a6169412819cc3a027c6a118f0537911145a30 that caused hangs in etracer
on 845s.
Bug #26557.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| e67c338b415c983bee570e6644b9684d8d1fc99b |
|
19-May-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Throttle after doing copyregion/swapbuffers round trip
Before we would throttle in the flush callback prior to round-tripping
to the server to do copyregion or swapbuffer. Now, instead just note
that we need to throttle and do it in intel_prepare_render(), which
will be called after receiving the response from the server but before
we start rendering the next frame. Even if the server also throttles
us in swapbuffer, this just makes the throttling a no-op when we hit
intel_prepare_render(). With that we can drop the
using_dri2_swapbuffers hack and just always throttle.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| b8b2670fef4790d650939fece8c7e6c7b76c3171 |
|
18-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add SF program disasm under INTEL_DEBUG=sf.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| c1423e34f910026d1c37a64e64d15277a4dd1258 |
|
14-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add program dumping for INTEL_DEBUG=gs.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 562e2d114ec0cba879463980522d1d54af9444e6 |
|
14-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Support INTEL_DEBUG=clip to dump the clip program.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| db2993faa0211b60efd46016de5d07110cb9777a |
|
11-May-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop viewport hack when we can
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| c4775a27e3aaa2006b98f225387499b79bc609ef |
|
10-May-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop intelFlush()
Now that intel_flush() deosn't use the needs_mi_flush argument, we can
finally drop one of the two flush functions.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 4b69100bdcf26dbb5be4d600b7ca5f5cdf6e8f20 |
|
27-Apr-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
dri: Add DRI entrypoints to create a context for a given API
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| cdcef6cbf4dd80047819e9098e34a3b98bd502a4 |
|
19-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
intel: Clean up chipset name and gen num for Ironlake
Rename old IGDNG to Ironlake, and set 'gen' number for
Ironlake as 5, so tracking the features with generation num
instead of special is_ironlake flag.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| ff6bce552a1522160c64d10677a36a7ad6cf5f88 |
|
30-Mar-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Remove redundant fields from struct intel_context
All these pointers are in the __DRIcontext struct, which we point to.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 864f2bd61d2bad31b49a680a168fc6d7c04d1de1 |
|
19-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add INTEL_DEBUG=glsl_force to force brw_wm_glsl.c.
I keep finding the desire to force this path to debug it instead of
cooking up goofy-looking testcases to do so.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| bb35000b4b6dfe60048b2f5d60bc102c4a7fd791 |
|
05-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove non-kernel-exec-fencing support.
Shaves 60k off the driver from removing the broken spans code. This
means we now require 2.6.29, which seems fair given that it's a year
old and we've removed support for non-KMS already in the last release
of 2D.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 298be2b028263b2c343a707662c6fbfa18293cb2 |
|
19-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Replace the _mesa_*printf() wrappers with the plain libc versions
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| d449627829e1a4a3250a1a723af2f4e3cd5fd194 |
|
18-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Implement the DRI2 invalidate function properly
This uses a stamp mechanisms to mark the DRI drawable as invalid.
Instead of immediately updating the buffers we just bump the drawable
stamp and call out to DRI2GetBuffers "later".
"Later" used to be at LOCK_HARDWARE time, and this patch brings back
callouts at the points where we used to call LOCK_HARDWARE. A new function,
intel_prepare_render(), is called where we used to call LOCK_HARDWARE,
and if the buffers are invalid, we call out to DRI2GetBuffers there.
This lets us invalidate buffers only when notified instead of on
every glViewport() call. If the loader calls the DRI invalidate
entrypoint, we disable viewport triggered buffer invalidation.
Additionally, we can clean up the old viewport mechanism a bit,
since we can just invalidate the buffers and not worry about
reentrancy and whatnot.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 5777dee02c6497207e6b4b9d68de072e7be7c06e |
|
11-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
i915: Drop intelScreenPrivate typedef and just call it struct intel_screen
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| f9439e4a4696b8bc5fcdf3ac664f5e8d446f6621 |
|
28-Jan-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove long-disabled meta readpixels, and associated meta support.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| a389d6bd566ba241a285c3a33039d5e964bc8f30 |
|
27-Jan-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove the remaining cliprects code from DRI1.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 7aed23c36288c2b343073d6d06ca0ea167805cd3 |
|
25-Jan-2010 |
Eric Anholt <eric@anholt.net> |
intel: Don't do client-side frame throttling with DRI2 SwapBuffers.
The server side does the throttling on our behalf now by putting the
client to sleep, so we don't need our previous hacks for limiting the
number of outstanding frames. Same effect as
7d4e674b212c9dc6408c13913a399bd4a2b9a1e3.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 8f7dfe302557eca6a48d03abc38bfc32dbe2ad8f |
|
20-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove dead note_fence vtbl hook.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| c6ef705e414c8e93ee471f50d15ada3492a9b067 |
|
11-Jan-2010 |
Jesse Barnes <jbarnes@virtuousgeek.org> |
Merge branch 'master' of ssh://people.freedesktop.org/~jbarnes/mesa
Conflicts due to DRI1 removal:
src/mesa/drivers/dri/intel/intel_context.c
src/mesa/drivers/dri/intel/intel_screen.c
|
| 7c50d29f7ced3d60e52ee0146d982b49ea421de2 |
|
08-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel/DRI2: add DRI2flushExtension support with invalidate hook
Needed to support the SwapBuffers code properly.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 2861d9200be15cc44e8825387d3bd79086523c67 |
|
02-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop more cliprect bookkeeping
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| a6e1d3edac90016ca9662ca0a9707a2d4fba1726 |
|
02-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Remove client-side vblank code
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| f55d0920cd8e504a09e3741716fc47381c03f6ac |
|
02-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop DRI1 static regions
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 01dc463e5d5513e059eea601710cd4babe02610d |
|
02-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop LOCK/UNLOCK_HARDWARE()
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| d61f07318c8678901b948fdaa8ccdf37aa3203e9 |
|
01-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Remove leftover __DRI{screen,drawable,context}Private references
As part of the DRI driver interface rewrite I merged __DRIscreenPrivate
and __DRIscreen, and likewise for __DRIdrawablePrivate and
__DRIcontextPrivate. I left typedefs in place though, to avoid renaming
all the *Private use internal to the driver. That was probably a
mistake, and it turns out a one-line find+sed combo can do the mass
rename. Better late than never.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 25024d948298a9f3f3210a0b91486f79a3917b0f |
|
31-Dec-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch'
Conflicts:
configs/darwin
src/gallium/auxiliary/util/u_clear.h
src/gallium/state_trackers/xorg/xorg_exa_tgsi.c
src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c67bb15d4e3da430d511444bd7d159ccb0c84b73 |
|
29-Dec-2009 |
Vinson Lee <vlee@vmware.com> |
intel: Silence compiler warnings.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| f67748038935e609aa85450b20d550b4813c9429 |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace some gen3 IS_* checks with context structure usage.
Shaves 400 bytes or so from i915_dri.so.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 0b87f143c466f7e5bd730895ee29f1cd20a68f9b |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_G4X() across the driver with context structure usage.
Saves ~2KB of code.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 1c96e85c9d6b8c636b0636f3320d1057ab5357b3 |
|
16-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.
Saves ~480 bytes of code.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 827ba44f6ee83ab21c6a2b09323f6f1df4a7d4c8 |
|
18-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove non-GEM support.
This really isn't supported at this point. GEM's been in the kernel for
a year, and the fake bufmgr never really worked.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 667760f53c16fae45ab29881c5ea12eef5fcda54 |
|
18-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove dead intel_context members and move some packing around.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| ee64347979b4e22976910cb97869887f7de4241c |
|
18-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove our special color packing macros and just use colormac.h.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| c4b7c47fe3135f852919cf2d4a2f64210e8cf125 |
|
18-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Pack colors for blit at blit time, rather than at ClearColor.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| cc39fcad89db2a4fc96b64915d42e5b1ac59d345 |
|
18-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i915: Remove dead meta_draw_quad code.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 1ffd0a77896d4921677f0717e6fa8708f6586eea |
|
13-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove some dead context structure fields.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| ded0ec1ea5db8e08b0bec8ac0d9d30f98e360003 |
|
12-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Use bo_map instead of subdata to upload the bits of constant buffer.
Saves CPU time, resulting in a 2.5% FPS win on ETQW.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 8e0f40d28777f1ae599a95312788fe29a0515a0d |
|
04-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing.
This should do all the things that MI_FLUSH did, but it can be pipelined
so that further rendering isn't blocked on the flush completion unless
necessary.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| caf3038123d6d29afd7d1f0cd6db98a2282c3ca1 |
|
26-Oct-2009 |
Eric Anholt <eric@anholt.net> |
Make a convenient int for what chipset generation we're on.
gen2/3/4 are easier to say than "8xx, 915-945/g33/pineview, 965/g45/misc",
and compares on generation are often easier than stringing together a bunch
of chipset checks.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| f8f40b53a6a4551630e25bfd7f6e12334bb0f3f8 |
|
29-Oct-2009 |
Eric Anholt <eric@anholt.net> |
i915: Implement min/max LOD clamping with the hardware.
This gets us expected behavior for clamping between mipmap levels, and
avoids relayout of textures for doing clamping.
Fixes piglit lodclamp-between.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| ab9d1011f5549502a4b960c2067cde69856a2719 |
|
23-Oct-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_6_branch'
|
| c24466c34e7aeb8aeda2455f6a688b99c44b10e2 |
|
23-Oct-2009 |
Brian Paul <brianp@vmware.com> |
intel: define INTEL_FALLBACK_DRIVER for drivers
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| ea659f891740fab1943eca219ffbdd5ed3d1906c |
|
23-Oct-2009 |
Brian Paul <brianp@vmware.com> |
intel: Fallback field is a bitmask, use GLbitfield
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 862a2a55b35d1dec9224b025a6e7a0cf8593a6a7 |
|
29-Jul-2009 |
Eric Anholt <eric@anholt.net> |
i915: Add optional support for ARB_fragment_shader under a driconf option.
Other vendors have enabled ARB_fragment_shader as part of OpenGL 2.0
enablement even on hardware like the 915 with no dynamic branching or
dFdx/dFdy support. But for now we'll leave it disabled because we don't
do any flattening of ifs or loops, which is rather restrictive.
This support is not complete, and may be unstable depending on your shaders.
It passes 10/15 of the piglit glsl tests, but hangs on glean glsl1.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 8b23755ce978247a92c00e390de2e459c0a9d5ad |
|
22-Sep-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove some dead metaops code.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| afd6141934a0fb52fc1739a2a9992db3ac34682b |
|
01-Sep-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add support for ARB_sync.
We currently weasel out of supporting the timeout parameter, but otherwise
this extension looks ready, and should make the common case happy.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 87946d206f64946af564f2086299e190883ef6ad |
|
14-Aug-2009 |
Tobias Doerffel <tobias.doerffel@gmail.com> |
intel: in intel_context struct use typedef for sarea struct
Using drm_i915_sarea_t instead of struct drm_i915_sarea seems to be
a common standard now, therefore fix it also in intel_context
structure. Additionally this silences a compiler warning:
intel_swapbuffers.c: In function `intelFixupVblank':
intel_swapbuffers.c:48: warning: initialization from incompatible pointer type
Signed-off-by: Tobias Doerffel <tobias.doerffel@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 922ef4a119ca9c7a8220843b47b890c277c29fc8 |
|
06-Aug-2009 |
Brian Paul <brianp@vmware.com> |
intel: minor context comments
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 0828579a658af01a64b5e699175dc9bbbedcd685 |
|
21-Jul-2009 |
Eric Anholt <eric@anholt.net> |
intel: Wait on the last swapbuffers to complete before queuing a new one.
This fixes jerkiness in doom3 and other apps since the kernel change to
throttle less absurdly, which led to a thundering herd of frames.
Because this is a rather minimal fix, there is at least one downside: If
the whole scene completes in one batchbuffer, we'll end up stalling the GPU.
Thanks to Michel Dänzer for suggesting using glFlush to signal frame end
instead of going to all the effort of adding a new DRI2 extension.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| f6f0e117a45a64464e49290ebc9f75b9a976070a |
|
15-Jul-2009 |
Dave Airlie <airlied@redhat.com> |
intel/radeon: add common metaops code.
Move all the metaops to a dri_metaops file and port radeon/intel
to use the new common meta ops code.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 94008088c1e6758a44a2f48c5a94db1f072d255a |
|
29-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Move note_unlock() implementation to the one place it's needed.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| df70d3049a396af3601d2a1747770635a74120bb |
|
20-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Also get the DRI2 front buffer when doing front buffer reading.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| b30dc2c66aeaad6661eef515a08a3da89aa07cb2 |
|
10-Jun-2009 |
Eric Anholt <eric@anholt.net> |
i915: Add an option for testing the effect of early Z in classic mode.
The early Z stuff is supposed to be unsafe without some more work in the
enable/disable path (in particular, how do we want to get it disabled on
the way out to the X Server?), but at the moment is 6% in OA.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 1ba96651e12b3c74fb9c8f5a61b183ef36a27b1e |
|
03-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add support for tiled textures.
This is about a 30% performance win in OA with high settings on my GM45,
and experiments with 915GM indicate that it'll be around a 20% win there.
Currently, 915-class hardware is seriously hurt by the fact that we use
fence regs to control the tiling even for 3D instructions that could live
without them, so we spend a bunch of time waiting on previous rendering in
order to pull fences off. Thus, the texture_tiling driconf option defaults
off there for now.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 165ae5e2fb57bdb64b4cf01271b4effeb811f675 |
|
04-Jun-2009 |
Eric Anholt <eric@anholt.net> |
i915: Don't rely on fence regs when we don't have to.
We're on the way to telling the kernel about when we need fence regs on our
objects or not, and this will cut the number of places needing them.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 8ec6e036792decf5149a209e51cb5e93ccc5c754 |
|
27-May-2009 |
Eric Anholt <eric@anholt.net> |
i915: Fall back on NPOT textured metaops on 830-class.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 3039acfc5db67f3935f9c30a9f17193ab52b20a9 |
|
13-May-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_5_branch'
Conflicts:
src/mesa/main/arrayobj.c
src/mesa/main/arrayobj.h
src/mesa/main/context.c
|
| 2e4e34689022ecfcc7dc107427db90cc52a94d63 |
|
13-May-2009 |
Brian Paul <brianp@vmware.com> |
intel: create a private gl_array_object for intel_clear_tris(), fix bug 21638
gl_array_object encapsulates a set of vertex arrays (see the
GL_APPLE_vertex_array_object extension).
Create a private gl_array_object for drawing the quad for intel_clear_tris()
so we don't have to worry about the user's vertex array state.
This fixes the no-op glClear bug #21638 and removes the need to call
_mesa_PushClientAttrib() and _mesa_PopClientAttrib().
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 1d663ae2925ffadf419ddbea9eca8d5706ea6510 |
|
08-May-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add a metaops version of glGenerateMipmapEXT/SGIS_generate_mipmaps.
In addition to being HW accelerated, it avoids the incorrect
(black) rendering of the mipmaps that SW was doing in fbo-generatemipmap.
Improves the performance of the mipmap generation and drawing in
fbo-generatemipmap by 30%.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| b6e94f71c2bfc63497e2c8265179f19babe87688 |
|
08-May-2009 |
Eric Anholt <eric@anholt.net> |
intel: Put the constant texcoords used in metaops into a vbo.
Make this be its own function for setup/teardown of the binding of these
texcoords. No performance difference in the engine demo (I just felt dirty
not using a VBO for this), and I think it should be more resilient to
interference from current GL state.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 2c30fd84dfa052949a117c78d932b58c1f88b446 |
|
10-Apr-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add support for argb1555, argb4444 FBOs and fix rgb565 fbo readpixels.
Also enable them all regardless of screen bpp, as 32 bpp what I've been
testing against, and haven't been able to detect any screen bpp-specific
troubles with them.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 43cf0d1eebb9f425e1a0e176394b64e2cb406709 |
|
06-Apr-2009 |
Ian Romanick <idr@freedesktop.org> |
intel / DRI2: Track and flush front-buffer rendering
Track two flags: whether or not front-buffer rendering is currently
enabled and whether or not front-buffer rendering has been enabled
since the last glFlush. If the second flag is set, the front-buffer
is flushed via a loader call back. If the first flag is cleared, the
second flag is cleared at this time.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kristian Høgsberg <krh@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 6b187cc8a5041fe2bba1ecc34aa86516ebe8b1b0 |
|
06-Apr-2009 |
Eric Anholt <eric@anholt.net> |
intel: Avoid dri2 GetBuffers round-trips for internal Viewport calls.
This gets us the savings for driver-internal viewport calls that
dd1c68f15123a889a3ce9d2afe724e272d163e32 was attempting, without relying
on Xlib internals or clients handling X events.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 40bc2748c2781600c748e546160bcc2aab637825 |
|
06-Mar-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add always_flush_batch driconf option for making small batchbuffers.
This can improve debugging with INTEL_DEBUG=batch,sync by giving smaller
batchbuffers.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| f3687284c12f34268172b9c60e2effd697162129 |
|
06-Mar-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add always_flush_cache driconf option for debugging cache flush failure.
I keep wanting to hack this knob in as a one-time thing, so it seemed useful
to have all the time.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 0d31e340f894fdf755945712668197cf09670222 |
|
05-Mar-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove dead flushing code.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 34683150878e0af0859c94d0c1f0c4bf8395b042 |
|
05-Mar-2009 |
Robert Ellison <papillo@vmware.com> |
i965: add software fallback for conformant 3D textures and GL_CLAMP
The i965 hardware cannot do GL_CLAMP behavior on textures; an earlier
commit forced a software fallback if strict conformance was required
(i.e. the INTEL_STRICT_CONFORMANCE environment variable was set) and
2D textures were used, but it was somewhat flawed - it could trigger
the software fallback even if 2D textures weren't enabled, as long
as one texture unit was enabled.
This fixes that, and adds software fallback for GL_CLAMP behavior with
1D and 3D textures.
It also adds support for a particular setting of the INTEL_STRICT_CONFORMANCE
environment variable, which forces software fallbacks to be taken *all*
the time. This is helpful with debugging. The value is:
export INTEL_STRICT_CONFORMANCE=2
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 84c8b5bbf980deea6322009354c3331dc5d5eb57 |
|
27-Jan-2009 |
Brian Paul <brianp@vmware.com> |
intel: move some driver functions around
A step toward consolidating i915/intel_state.c and i965/intel_state.c
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 723648f2ee2a8e529063c9da84e9dff9c8c6be99 |
|
26-Jan-2009 |
Brian Paul <brianp@vmware.com> |
intel: save/restore GL matrix mode in intel_meta_set_passthrough_transform(), intel_meta_restore_transform()
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 4006c5e4526a1cdb910500764590e39d32750967 |
|
26-Jan-2009 |
Brian Paul <brianp@vmware.com> |
intel: move intelInitExtensions() and related code into new intel_extensions.c
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| bfebeffc0045266d354a36968336337e099a9f27 |
|
31-Dec-2008 |
Eric Anholt <eric@anholt.net> |
intel: Share passthrough transform setup between glBitmap and glDrawPixels.
The DrawPixels path was missing glViewport care, so blender's toolbar icons
would go to the wrong places.
Bug #19118.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| e1a92175542c6645c23cc78f2a4fcd36dd0235e6 |
|
31-Dec-2008 |
Eric Anholt <eric@anholt.net> |
intel: Add support for glBitmap as metaops using GL calls.
This lets us avoid software fallbacks when clients forget to turn some state
off (engine demo) or just do crazy things to test conformance (OGLC).
This should probably be brought into mesa generic code so other drivers can
make use of it.
Bug #19016.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| b359350017a8f0328912f19d233bcdcc256aded1 |
|
20-Dec-2008 |
Dave Airlie <airlied@redhat.com> |
Remove third buffer support from Mesa.
This is part of the deprecated pageflipping infrastructure.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| cd031749a75883a6fbf8fb7bf989b77a7c705819 |
|
28-Nov-2008 |
Dave Airlie <airlied@redhat.com> |
intel: restore old vertex submit paths for i8xx hardware.
Intel docs state that only 830/845 have VBOs, 855/865 don't. So
lets just not use them on i8xx at all.
This restores the old pre-vbo code and uses it on all 8xx hw.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 2adef553f2549e30b4a1894e7f9077ac339ea61c |
|
14-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i915: Don't overwrite i915's Viewport function from generic code.
Instead, have i965 and i915 both call the generic function from their Viewport.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 0cade4de4f74f6b0e86fb6622e2fc370c73fd840 |
|
20-Oct-2008 |
Eric Anholt <eric@anholt.net> |
intel: Don't keep intel->pClipRects, and instead just calculate it when needed.
This avoids issues with dereferencing stale cliprects around intel_draw_buffer
time. Additionally, take advantage of cliprects staying constant for FBOs and
DRI2, and emit cliprects in the batchbuffer instead of having to flush batch
each time they change.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 7d99ddcb2bb09f1f54d91e6e20e42d217a5bccdf |
|
26-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: Fix a number of memory leaks on context destroy.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 3628185f566e178a12b493fb89abf52b4b281f99 |
|
06-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| a04aeea5c016530d7371e032438a0a8fa2c0d7f6 |
|
03-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: Fix prototype warning.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| f56b569e9af356c11869ee49a4669bb01b75397e |
|
13-Aug-2008 |
Kristian Høgsberg <krh@redhat.com> |
DRI2: Drop sarea, implement swap buffers in the X server.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| d2796939f18815935c8fe1effb01fa9765d6c7d8 |
|
08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Update to new check_aperture API for classic mode.
To do this, I had to clean up some of 965 state upload stuff. We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| 2e841880cfc1006a2818d4a8bfefd21136dc39a9 |
|
11-Jul-2008 |
Eric Anholt <eric@anholt.net> |
drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| e74f54793e45dd2e36474f6fc527456647f32efd |
|
02-Jul-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode.
It turns out that it's not just deviceID dependent, and there's some additional
undefined factor that determines the bit 6 swizzling. It's now controllable
with swizzle_mode=[012] until we get a response on how to automatically detect.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|
| f6abe8f0f2fba3073b58b96ed38aae163c765b4a |
|
24-Jun-2008 |
Eric Anholt <eric@anholt.net> |
Merge commit 'origin/master' into drm-gem
|
| a42dac187973cbc17be6c59db89264cbc935ab91 |
|
24-Jun-2008 |
Eric Anholt <eric@anholt.net> |
i915: Accumulate the VB into a local buffer and subdata it in.
This lets GEM use pwrite, for an additional 4% or so speedup.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
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| 62d66caeba786f01f6159c980fda79606afe4c61 |
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21-Jun-2008 |
Eric Anholt <eric@anholt.net> |
i915: Convert to using VBs instead of inline prims.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
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| ba97ed2b743ba0b6631e0fbcf2ab12afe885f87c |
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21-Jun-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
replace __inline and __inline__ with INLINE macro
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
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| 4b5b008d54e86ac4f0a2176429d062100978ca8c |
|
03-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert drivers to using libdrm bufmgr code.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
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| eb10cdc838fc31ea2cf59f556f6f7d8b072f5bae |
|
02-May-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Fix build for GEM. TTM is now disabled, and fencing is gone.
Fencing was used in two places: ensuring that we didn't get too many frames
ahead of ourselves, and glFinish. glFinish will be satisfied by waiting on
buffers like we would do for CPU access on them. The "don't get too far ahead"
is now the responsibility of the execution manager (kernel).
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
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| fcb7cb9e72ecac7c165a3a6ed7a033e2e6793a26 |
|
13-Mar-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] multiple rendering target support
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
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| fe91c05b5494b889c8adda77ff562712116d2e59 |
|
05-Mar-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Add a driconf option to cache freed buffer objects for reuse.
This is defaulted off as it has potentially large memory costs for a modest
performance gain. Ideally we will improve DRM performance to the point where
this optimization is not worth the memory cost in any case, or find some
middle ground in caching only limited numbers of certain buffers. For now,
this provides a modest 4% improvement in openarena on GM965 and 10% in openarena
on GM945.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
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| 60c0f09abb9421de359cd92e094a943d650fc7fa |
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27-Feb-2008 |
Kristian Høgsberg <krh@redhat.com> |
intel: Always use intelInitExtensions() for initializing extensions.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
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| c99fa92ff84e927c82e1231d96921fda9a2b0852 |
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22-Feb-2008 |
Kristian Høgsberg <krh@redhat.com> |
Merge {i915,i965}/intel_context.h as intel/intel_context.h
/external/mesa3d/src/mesa/drivers/dri/intel/intel_context.h
|