| c8580eefbc2dc1a563a3a327bba6b1e5cc9aca5c |
|
04-Dec-2014 |
hding3 <haitao.ding@intel.com> |
wrs_core: enable meta data mode on L
BZ: 230000
Bug:18575549
Ignore buffer return when format change happens
for meta data mode.
The patch was ported from imin_legacy branch: https://android.intel.com:443/291947
Change-Id: I9226eb87d273d25a3c8152d0e5837a29bb574ac1
Signed-off-by: hding3 <haitao.ding@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 3f7ceee13aa17ae32d4263aed2ce67eb9a37c58b |
|
24-Jul-2014 |
ywan171 <yi.a.wang@intel.com> |
remove the warning in wrs_core
BZ: 209178
remove the warning in wrs_core
Signed-off-by: ywan171 <yi.a.wang@intel.com>
Change-Id: I5655dcc283325cf7da5e0b088887e63cd24fb056
Signed-off-by: ywan171 <yi.a.wang@intel.com>
Reviewed-on: https://android.intel.com/220500
Reviewed-by: Fourdan, Olivier <olivier.fourdan@intel.com>
Tested-by: Fourdan, Olivier <olivier.fourdan@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 11edd8693709808ef6b89b3f58970ea64bf95486 |
|
13-May-2014 |
ywan171 <yi.a.wang@intel.com> |
wrs_core: notify error event if enabled complete event is triggered by freeing buffer
BZ: 190818
notify error event instead if enabled complete event is triggered by freeing buffer
Change-Id: I6997dbf7f38ff8c3653d14da5425db5ba665179e
Signed-off-by: ywan171 <yi.a.wang@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| b8964d8a892a8f105ac047d9a4d56300cf35d8c2 |
|
14-May-2014 |
Tianmi Chen <tianmi.chen@intel.com> |
wrs_omxil_core: set stride and sliceHeight in port definition
BZ: 196039
set stride and sliceHeight in port definition.
Change-Id: I83690471557471d66f7ef316d2bb7ee426aeae54
Signed-off-by: Tianmi Chen <tianmi.chen@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 84ce850bc47dcadb25c6357ec4331ebd47df626e |
|
21-Apr-2014 |
bolunliu <bolun.liu@intel.com> |
fix a tiny issue in Portbase
BZ: 189356
fix a tiny compile issue in Portbase when LOGV was enable
Change-Id: I7019146a540f9419171d3190f1a3d18130a3afa3
Signed-off-by: bolunliu <bolun.liu@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 41e08b779bbfab77f59765aa470aa93e2d81b877 |
|
24-Feb-2014 |
ywan171 <yi.a.wang@intel.com> |
wrs_core: add timeout waitevent in video decoder to avoid dead lock when state changes from disable to enable
BZ: 164253
When output port state changes from disable to enable, the HAL will wait gralloc buffers set from OMX client.
If dequeuebuffer fails in omx client, the video decoder HAL will fall into dead wait, and error will occur in destroying
OMX node. add timeout waitevent in wrs_core for video decoder to avoid dead lock
Change-Id: I604ca37879d95bfd5cdfc2512043c1c60a74d415
Signed-off-by: ywan171 <yi.a.wang@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| a4315bcc3603ce74c2faeb4b81563dd3396cbd64 |
|
24-Dec-2013 |
gji2 <guoliang.ji@intel.com> |
Fix the middleware encode patch impact on decode module issue.
BZ: 160888
Fix the middleware encode patch impact on decode module issue.
Change-Id: I37d4e6d1bdbece72df768578311d108ec5df7a64
Signed-off-by: gji2 <guoliang.ji@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| a081918af785d476df2da1342eabe245eab468d0 |
|
05-Dec-2013 |
Zhao Liang <leo.zhao@intel.com> |
Change omx core mechanism to allow encoder working more time
BZ: 150664
for encoder case, if either bufferq or retainedbufferq is not empty
core will schedule encoder working, and inport buffer may be null if
only retainedbufferq has frame.
Change-Id: Id347f3843d806c41176dec49f543963204603e29
Signed-off-by: Zhao Liang <leo.zhao@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 78c1837ebe200a58aebed8bad480064da909d6ff |
|
03-Dec-2013 |
Liu Bolun <bolun.liu@intel.com> |
Add "OMX_COLOR_FormatUnused" case in getFrameBufSize
BZ: 154696
Add "OMX_COLOR_FormatUnused" case in getFrameBufSize to fix WIFI Display break issue.
Change-Id: Ib6c0cf672e104fae19432bef9d56c8f9a63bf6f4
Signed-off-by: Liu Bolun <bolun.liu@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 64e2d27bd6b5c91266349730c4fe00a9f07bee81 |
|
06-Nov-2013 |
Dan Liang <dan.liang@intel.com> |
wrs_omxil_core: use pOutputPortPrivate to report error
BZ: 147912
1)use pOutputPortPrivate to report error
2)define data structure OMX_VIDEO_CONFIG_INTEL_ERROR_REPORT
Change-Id: Id2e50570cf164cb441fbf9866e8c0749f19f7313
Signed-off-by: Dan Liang <dan.liang@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 6b034a28c5a1731a2997f3fcbc07bb11338dc04f |
|
27-Oct-2013 |
Weian Chen <weian.chen@intel.com> |
omx-core: set pInputPortPrivate to NULL by default
BZ: 148092
pInputPortPrivate will be used by webRTC to contain the
rotation information, by default it should be NULL, remove
the useless code related to pInputPortPrivate in base class
Change-Id: I49ebd9b3867a186848c8d3a9fd44965048776974
Signed-off-by: Weian Chen <weian.chen@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 43d2bde2a903886197f00f077218f13014bf8373 |
|
30-Oct-2013 |
sameer <sameer.kibey@intel.com> |
[wrs_core]Fix hang when port disable called for empty port.
BZ: 148867
This issue was found when using gstreamer with Intel OMX Core
using the gst-omx plugin. In gst-omx playback, when transitioning
component to idle state the output port is disabled. The call to
disable output port hangs in WaitPortBufferCompletion() in the OMX
IL Core. This is due to a bug where WaitPortBufferCompletion() waits for
buffer free operation to complete on an empty port. Since port
is empty buffer free will never be called. Added check on buffer
count before doing the wait to avoid the hang.
Change-Id: If34c3388be978bcec5d33100858d343468d835f9
Signed-off-by: Sameer Kibey <sameer.kibey@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 5ab2f45a95344b12cad43f277a730c8679b42171 |
|
17-Jun-2013 |
Dan Liang <dan.liang@intel.com> |
[PDK MR2 ABSP] remove duplicate omx header file between khronos and google framework
BZ: 117349
khronos omx will reference google framework to avoid conflict causing by the
inconformity, the conflict will cause video record doesnot work in PDK
Change-Id: I6762f097e91a47ba820d03923d6141311de53ff6
Signed-off-by: ywan171 <yi.a.wang@intel.com>
Signed-off-by: Dan Liang <dan.liang@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| c3e26983a72fa51f0dff98bc66234b73f74adc17 |
|
19-Nov-2012 |
wfeng6 <wei.feng@intel.com> |
[PORT FROM MAIN] Report errors when failing to set the input port size
BZ: 68835
The patch allows to set the input port size according to the size
required by OMXCodec. When the required size is larger than the
threshold, a OMX_ErrorBadParameter error will be reported to
OMXCodec.
Change-Id: I648a580e35d0c023b14f3313b48a08a1b4dc60cd
Signed-off-by: wfeng6 <wei.feng@intel.com>
Reviewed-on: http://android.intel.com:8080/76393
Tested-by: Tong, BoX <box.tong@intel.com>
Reviewed-by: Tong, BoX <box.tong@intel.com>
Reviewed-by: cactus <cactus@intel.com>
Tested-by: cactus <cactus@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 229ae5acfb89e9c1559c0394190e77ca6f23f24b |
|
24-Jul-2012 |
Zhao Liang <leo.zhao@intel.com> |
Add new interface in portbase to set if pBuffer is 4k aligned in AllocateBuffer
BZ: 48107
This change is part of Video enhancement modification on video buffer sharing, it is
used to keep omx port buffer aligned in 4K when in RAW mode, HW has this limitation on
malloc memory wrapping into surface
Change-Id: Ifdc639729c24fa218fa2438903a0f32d0880192f
Signed-off-by: Zhao Liang <leo.zhao@intel.com>
Reviewed-on: http://android.intel.com:8080/58215
Reviewed-by: Qiu, Junhai <junhai.qiu@intel.com>
Reviewed-by: Yuan, Shengquan <shengquan.yuan@intel.com>
Reviewed-by: Ji, Guoliang <guoliang.ji@intel.com>
Reviewed-by: Ding, Haitao <haitao.ding@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: Ding, Haitao <haitao.ding@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| ab52c3ff446a8712299a0d866f8ac8372491cdcb |
|
29-Feb-2012 |
Andy Qiu <junhai.qiu@intel.com> |
Extend middleware to support secure video playback.
BZ: 29937
Add interface to enable customized memory allocation.
Change-Id: I67931e5de00ff873fdc224c8015792ee31dca82d
Signed-off-by: Andy Qiu <junhai.qiu@intel.com>
Reviewed-on: http://android.intel.com:8080/36929
Reviewed-by: buildbot <buildbot@intel.com>
Reviewed-by: Vehmanen, Kai <kai.vehmanen@intel.com>
Reviewed-by: Ding, Haitao <haitao.ding@intel.com>
Tested-by: Ding, Haitao <haitao.ding@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| ecc877a1dd44921dff3f300bc5559841f0c44ac6 |
|
09-Apr-2012 |
ywan171 <yi.a.wang@intel.com> |
wrs_omxil_core: enhance wrs_omxil_core to handle the case that resolution in container is diff from ES resolution
BZ: 25724 29844 28316
enhance wrs_omxil_core to handle the case that resolution in container is diff from ES resolution
1: if the resolution in container is larger than real ES resolution, return the correct crop
info to omxcodec to set the proper region for display
2: if the resolution in container is smaller than real ES resolution, Graphic buffer in omxcodec
should be reallocated and reset graphic related info to OMXIL and libmix, va should be restart.
Change-Id: I8adfde55d850bebc8cee11b73e624d57f039727c
Signed-off-by: ywan171 <yi.a.wang@intel.com>
Reviewed-on: http://android.intel.com:8080/42769
Reviewed-by: Qiu, Junhai <junhai.qiu@intel.com>
Reviewed-by: Ding, Haitao <haitao.ding@intel.com>
Tested-by: Ding, Haitao <haitao.ding@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 705c231d1e4ff148d8cec637288d9ad41429f0e3 |
|
22-Feb-2012 |
Weian Chen <weian.chen@intel.com> |
wrs-omx-core: code cleanup along with one Queue buffer management support
BZ: 24552
code cleanup along with one Queue buffer management support and remove two Queue
method (from Andy)
Signed-off-by: Weian Chen <weian.chen@intel.com>
Change-Id: I9b2109b45572492209ff4fa096e98c5442c3bfbd
Reviewed-on: http://android.intel.com:8080/36140
Reviewed-by: Chen, Weian <weian.chen@intel.com>
Reviewed-by: Qiu, Junhai <junhai.qiu@intel.com>
Reviewed-by: Ding, Haitao <haitao.ding@intel.com>
Tested-by: Ding, Haitao <haitao.ding@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 34277d8b1ca48a932e7b17ba331c29f040ba0838 |
|
19-Dec-2011 |
xiao <fengx.xiao@intel.com> |
Enable native buffer mode for ICS in wrs core
,clean buffer id mode related code
BZ: 18370
Signed-off-by: xiao <fengx.xiao@intel.com>
Change-Id: I657ac61aeaaaffdbacde3afd9743a9ddeed29588
Reviewed-on: http://android.intel.com:8080/27892
Reviewed-by: Ding, Haitao <haitao.ding@intel.com>
Tested-by: Ding, Haitao <haitao.ding@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 44e493bfd5e5abeadd4431e294d3108235bdeb29 |
|
17-Nov-2011 |
Shuo Liu <shuo.liu@intel.com> |
modify wrs omx core base to set up ics hw video playback
1. support param extension 'OMX.Intel.Index.BufferIDMode'
2. refine the port setting changed event logic
Change-Id: I582cb0fff6ce1c8e71a4ef3536d71bed51ef1915
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| f17c91825c5ef8ac1dd211e8f641b3851dccbc4c |
|
07-Apr-2011 |
xli111 <xiaowei.a.li@intel.com> |
Calculate the frame size according to color, height and width of the frame
Change-Id: Id3b900e2372ffff50032b88b872ef8cc9f44fdf0
Signed-off-by: xli111 <xiaowei.a.li@intel.com>
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 2f6e87e64736666857c1bbe2cb0692c1f4e56508 |
|
26-Feb-2010 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
copyright: apply Apache License, Version 2.0
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 6f700f4332f1c3aebf3b5af7bb3087ee9091abca |
|
31-Dec-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: flush port in ReportPortSettingsChanged
it prevents a component from processing buffers instantly by flushing the port
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 6bda193e1851c89a63c0cda1992de30c1a1c4716 |
|
30-Dec-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: fix debug messages
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 3ca48681b349388346b10abce74c98497d231d04 |
|
30-Dec-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add an Interface for sending OMX_EventPortSettingsChanged
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 37787374d75727678e1f9d19191fdad363ee6c54 |
|
17-Dec-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add GetPortBufferCount for getting allocated buffer header count
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 1e23923a42d574088787d8bed30df25f032e3ffb |
|
17-Dec-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: fix for retaining buffer
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 30bd6062e4b295f5f7bcaeb98165065310d29269 |
|
28-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
misc: add windriver standard copyright
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 515117111f4aff7141e1bd07e7d42065ea2fee6c |
|
21-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: fix bug, missing nBufferSize
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 57a49e4dad592011ea29a58268ddc6d817b0b69b |
|
21-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add debug messages
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| f4ab90019707fb84477f62dd3093eaff0ac466eb |
|
19-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: remove audio param from portbase class
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| e4197969e018f1f455d8a99ebabd51994b150506 |
|
16-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
misc: add copyright and author
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 6eef19eccd390d878724188ac5b62f4656a97110 |
|
16-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: fix minor, make more clear variable name in TransState
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| ff8337cbee32831a09989af92174d2cde83cf9f5 |
|
15-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: trylock in IsEnabled to avoid deadlock
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 3759c620f3e8325d1fdd741caad7c397e797ad2c |
|
14-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port,component: make clear parameter's role (read-only field)
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 5435027850dee5fe18425ed8d6513d551914d29b |
|
14-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add port[audio/video/image/other].[h/cpp] files
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 904a08909b5c3870414fde9faec0d74d0edd536c |
|
13-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add Audio/Video/Image/Other port class
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 76e479a9ee63cff7cf200aceb2f52296fe63c588 |
|
14-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add new constructor having portdefinition as its paramter
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| d6d95fe6be9fec1e85a1630bbf2a004f4396fa41 |
|
14-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: portdefinition replaces portparam
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 6c7f4263fbe4a642fb0a5c21b9e98c5c59c05468 |
|
14-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: fix minor, portdefinition not to allocated by malloc
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| f200e5f7a1350f3e20eb73836578ced68257b27d |
|
14-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:portbase: fix bug, SetPortDefinition
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 2b3ec7d86622ed1945c087fb73e93338bc7acd64 |
|
13-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add RetainThisBuffer to retain a buffer in CBase::Work
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 21f3c554c44d0d9404edcf20b7688f0d909f2e75 |
|
12-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: use state for IsEnabled
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| df459a0924eb9309157e4bffa9fe26d0513b800b |
|
12-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add TransState for port state set (enable/disable)
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 4571ebc981a6aa18db934972737de5a6e764f78d |
|
12-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: unused variable(state)
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 5e6d63b7252c7bc59567ea764b1b30b76554dcd4 |
|
09-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add Push/PopMark
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 4f4d5a8c4138b7ebfa624eaad8dea29332ed97a0 |
|
08-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add GetPortDirection
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 8b0c69f6315328521b722a6ceb19f354e867124a |
|
07-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add Set/GetPorDefinition that will replace Set/GetPortParam
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 3e70358f4893dffa18a9edf60e02fe4c017328de |
|
06-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:component,port: fix bug, state and param check in CBaseAllocate/UseBuffer
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| b2b1b8e0c1425cde2025791cfb74d9053170845c |
|
07-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add IsEnabled() for checking if a port's enabled.
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 47f587ac0f888f2c3c5643bf04fe4f699467a66a |
|
06-Oct-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:component: check ppBufferHdr and initialze with nil in Allocate/UseBuffer
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
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| fa693d49884f9188809c3a185ecd4cd38a878cb7 |
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25-Sep-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add FlushPort() for flushing buffers not under processing
It must be called holding ports big lock
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
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| f1d4ffbc89d682d76fe26c7f9fa956e4936c6b4d |
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25-Sep-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: implement ReturnThisBuffer()
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
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| cd27ef4881e3b8c9b1ff51a320d84ef71f522e90 |
|
25-Sep-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: fix bug, initialize owner with null
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
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| 19b0e5f37c63579e9ad52b2538cddb90d601775a |
|
25-Sep-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add SetCallbacks() accessor for ReturnThisBuffer()
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 7951efc74d2bac005b683460c159f34403a355b1 |
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25-Sep-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add BufferQueue functions
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| ffd9bf0e373ec1dc90cbaf2e772958b4493da6eb |
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25-Sep-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: check component's state in Use/Allocate/FreeBuffer
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 65f90f13a4ae2f113daf17558f01ffda1a0d05af |
|
25-Sep-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add GetOwnerState to get component's state
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 7b94bb78335b52b812d8b4137ce80799bb6b9125 |
|
25-Sep-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add owner(OMX_COMPONENTTYPE), accessors
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 6fc911638847488e09f42bdd125fbb79fc754cbd |
|
25-Sep-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: introduce WaitPortBufferCompletion
it' for buffer header allocation/deallocation
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| 974e5777ef2f549722c11ef999d5bb52bfcf199a |
|
25-Sep-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: implement Use/Allocate/FreeBuffer
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| cf575e55ba6597c77cf2413245e3f626f75b5005 |
|
25-Sep-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add Use/Allocate/FreeBuffer interface
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| a85b1f78b03f7027fe94d624ff1b54de9e7d5dad |
|
25-Sep-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: returns const pointer for Get*PortParam()
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| cf05610bceb8d988f80ec9696104a8afceb1edfd |
|
25-Sep-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add members & methods relative to parameter
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|
| c8c36c18719f55a4fbb3c1efbad24a3644c0d54e |
|
25-Sep-2009 |
Ho-Eun Ryu <ho-eun.ryu@windriver.com> |
base:port: add portbase class
/hardware/intel/common/wrs_omxil_core/base/src/portbase.cpp
|