Cross Reference: /art/compiler/dex/quick/mips/int

Lines Matching refs:rl_src2
45                              RegLocation rl_src2) {
47   rl_src2 = LoadValueWide(rl_src2, kCoreReg);
51   NewLIR3(kMipsSlt, t0.GetReg(), rl_src1.reg.GetHighReg(), rl_src2.reg.GetHighReg());
52   NewLIR3(kMipsSlt, t1.GetReg(), rl_src2.reg.GetHighReg(), rl_src1.reg.GetHighReg());
55   NewLIR3(kMipsSltu, t0.GetReg(), rl_src1.reg.GetLowReg(), rl_src2.reg.GetLowReg());
56   NewLIR3(kMipsSltu, t1.GetReg(), rl_src2.reg.GetLowReg(), rl_src1.reg.GetLowReg());
266                       RegLocation rl_src2, bool is_div, bool check_zero) {
396                              RegLocation rl_src1, RegLocation rl_src2) {
398   rl_src2 = LoadValueWide(rl_src2, kCoreReg);
408   OpRegRegReg(kOpAdd, rl_result.reg.GetLow(), rl_src2.reg.GetLow(), rl_src1.reg.GetLow());
410   OpRegRegReg(kOpAdd, t_reg, rl_src2.reg.GetHigh(), rl_src1.reg.GetHigh());
411   NewLIR3(kMipsSltu, rl_result.reg.GetHighReg(), rl_result.reg.GetLowReg(), rl_src2.reg.GetLowReg());
418                              RegLocation rl_src1, RegLocation rl_src2) {
420   rl_src2 = LoadValueWide(rl_src2, kCoreReg);
431   NewLIR3(kMipsSltu, t_reg.GetReg(), rl_src1.reg.GetLowReg(), rl_src2.reg.GetLowReg());
432   OpRegRegReg(kOpSub, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), rl_src2.reg.GetLow());
433   OpRegRegReg(kOpSub, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh());
440                                  RegLocation rl_src2) {
444       GenAddLong(opcode, rl_dest, rl_src1, rl_src2);
448       GenSubLong(opcode, rl_dest, rl_src1, rl_src2);
451       GenNegLong(rl_dest, rl_src2);
459   Mir2Lir::GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2);
637                                     RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
639   GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2);