Cross Reference: /art/compiler/utils/x86_64/assembler_x86

Lines Matching refs:src
129 void X86_64Assembler::movq(CpuRegister dst, CpuRegister src) {
132   EmitRex64(src, dst);
134   EmitRegisterOperand(src.LowBits(), dst.LowBits());
138 void X86_64Assembler::movl(CpuRegister dst, CpuRegister src) {
140   EmitOptionalRex32(dst, src);
142   EmitRegisterOperand(dst.LowBits(), src.LowBits());
146 void X86_64Assembler::movq(CpuRegister dst, const Address& src) {
148   EmitRex64(dst, src);
150   EmitOperand(dst.LowBits(), src);
154 void X86_64Assembler::movl(CpuRegister dst, const Address& src) {
156   EmitOptionalRex32(dst, src);
158   EmitOperand(dst.LowBits(), src);
162 void X86_64Assembler::movq(const Address& dst, CpuRegister src) {
164   EmitRex64(src, dst);
166   EmitOperand(src.LowBits(), dst);
170 void X86_64Assembler::movl(const Address& dst, CpuRegister src) {
172   EmitOptionalRex32(src, dst);
174   EmitOperand(src.LowBits(), dst);
185 void X86_64Assembler::movzxb(CpuRegister dst, CpuRegister src) {
187   EmitOptionalByteRegNormalizingRex32(dst, src);
190   EmitRegisterOperand(dst.LowBits(), src.LowBits());
194 void X86_64Assembler::movzxb(CpuRegister dst, const Address& src) {
196   EmitOptionalByteRegNormalizingRex32(dst, src);
199   EmitOperand(dst.LowBits(), src);
203 void X86_64Assembler::movsxb(CpuRegister dst, CpuRegister src) {
205   EmitOptionalByteRegNormalizingRex32(dst, src);
208   EmitRegisterOperand(dst.LowBits(), src.LowBits());
212 void X86_64Assembler::movsxb(CpuRegister dst, const Address& src) {
214   EmitOptionalByteRegNormalizingRex32(dst, src);
217   EmitOperand(dst.LowBits(), src);
221 void X86_64Assembler::movb(CpuRegister /*dst*/, const Address& /*src*/) {
226 void X86_64Assembler::movb(const Address& dst, CpuRegister src) {
228   EmitOptionalByteRegNormalizingRex32(src, dst);
230   EmitOperand(src.LowBits(), dst);
243 void X86_64Assembler::movzxw(CpuRegister dst, CpuRegister src) {
245   EmitOptionalRex32(dst, src);
248   EmitRegisterOperand(dst.LowBits(), src.LowBits());
252 void X86_64Assembler::movzxw(CpuRegister dst, const Address& src) {
254   EmitOptionalRex32(dst, src);
257   EmitOperand(dst.LowBits(), src);
261 void X86_64Assembler::movsxw(CpuRegister dst, CpuRegister src) {
263   EmitOptionalRex32(dst, src);
266   EmitRegisterOperand(dst.LowBits(), src.LowBits());
270 void X86_64Assembler::movsxw(CpuRegister dst, const Address& src) {
272   EmitOptionalRex32(dst, src);
275   EmitOperand(dst.LowBits(), src);
279 void X86_64Assembler::movw(CpuRegister /*dst*/, const Address& /*src*/) {
284 void X86_64Assembler::movw(const Address& dst, CpuRegister src) {
287   EmitOptionalRex32(src, dst);
289   EmitOperand(src.LowBits(), dst);
293 void X86_64Assembler::leaq(CpuRegister dst, const Address& src) {
295   EmitRex64(dst, src);
297   EmitOperand(dst.LowBits(), src);
301 void X86_64Assembler::movss(XmmRegister dst, const Address& src) {
304   EmitOptionalRex32(dst, src);
307   EmitOperand(dst.LowBits(), src);
311 void X86_64Assembler::movss(const Address& dst, XmmRegister src) {
314   EmitOptionalRex32(src, dst);
317   EmitOperand(src.LowBits(), dst);
321 void X86_64Assembler::movss(XmmRegister dst, XmmRegister src) {
324   EmitOptionalRex32(dst, src);
327   EmitXmmRegisterOperand(src.LowBits(), dst);
331 void X86_64Assembler::movd(XmmRegister dst, CpuRegister src) {
334   EmitOptionalRex32(dst, src);
337   EmitOperand(dst.LowBits(), Operand(src));
341 void X86_64Assembler::movd(CpuRegister dst, XmmRegister src) {
344   EmitOptionalRex32(src, dst);
347   EmitOperand(src.LowBits(), Operand(dst));
351 void X86_64Assembler::addss(XmmRegister dst, XmmRegister src) {
354   EmitOptionalRex32(dst, src);
357   EmitXmmRegisterOperand(dst.LowBits(), src);
361 void X86_64Assembler::addss(XmmRegister dst, const Address& src) {
364   EmitOptionalRex32(dst, src);
367   EmitOperand(dst.LowBits(), src);
371 void X86_64Assembler::subss(XmmRegister dst, XmmRegister src) {
374   EmitOptionalRex32(dst, src);
377   EmitXmmRegisterOperand(dst.LowBits(), src);
381 void X86_64Assembler::subss(XmmRegister dst, const Address& src) {
384   EmitOptionalRex32(dst, src);
387   EmitOperand(dst.LowBits(), src);
391 void X86_64Assembler::mulss(XmmRegister dst, XmmRegister src) {
394   EmitOptionalRex32(dst, src);
397   EmitXmmRegisterOperand(dst.LowBits(), src);
401 void X86_64Assembler::mulss(XmmRegister dst, const Address& src) {
404   EmitOptionalRex32(dst, src);
407   EmitOperand(dst.LowBits(), src);
411 void X86_64Assembler::divss(XmmRegister dst, XmmRegister src) {
414   EmitOptionalRex32(dst, src);
417   EmitXmmRegisterOperand(dst.LowBits(), src);
421 void X86_64Assembler::divss(XmmRegister dst, const Address& src) {
424   EmitOptionalRex32(dst, src);
427   EmitOperand(dst.LowBits(), src);
431 void X86_64Assembler::flds(const Address& src) {
434   EmitOperand(0, src);
445 void X86_64Assembler::movsd(XmmRegister dst, const Address& src) {
448   EmitOptionalRex32(dst, src);
451   EmitOperand(dst.LowBits(), src);
455 void X86_64Assembler::movsd(const Address& dst, XmmRegister src) {
458   EmitOptionalRex32(src, dst);
461   EmitOperand(src.LowBits(), dst);
465 void X86_64Assembler::movsd(XmmRegister dst, XmmRegister src) {
468   EmitOptionalRex32(dst, src);
471   EmitXmmRegisterOperand(src.LowBits(), dst);
475 void X86_64Assembler::addsd(XmmRegister dst, XmmRegister src) {
478   EmitOptionalRex32(dst, src);
481   EmitXmmRegisterOperand(dst.LowBits(), src);
485 void X86_64Assembler::addsd(XmmRegister dst, const Address& src) {
488   EmitOptionalRex32(dst, src);
491   EmitOperand(dst.LowBits(), src);
495 void X86_64Assembler::subsd(XmmRegister dst, XmmRegister src) {
498   EmitOptionalRex32(dst, src);
501   EmitXmmRegisterOperand(dst.LowBits(), src);
505 void X86_64Assembler::subsd(XmmRegister dst, const Address& src) {
508   EmitOptionalRex32(dst, src);
511   EmitOperand(dst.LowBits(), src);
515 void X86_64Assembler::mulsd(XmmRegister dst, XmmRegister src) {
518   EmitOptionalRex32(dst, src);
521   EmitXmmRegisterOperand(dst.LowBits(), src);
525 void X86_64Assembler::mulsd(XmmRegister dst, const Address& src) {
528   EmitOptionalRex32(dst, src);
531   EmitOperand(dst.LowBits(), src);
535 void X86_64Assembler::divsd(XmmRegister dst, XmmRegister src) {
538   EmitOptionalRex32(dst, src);
541   EmitXmmRegisterOperand(dst.LowBits(), src);
545 void X86_64Assembler::divsd(XmmRegister dst, const Address& src) {
548   EmitOptionalRex32(dst, src);
551   EmitOperand(dst.LowBits(), src);
555 void X86_64Assembler::cvtsi2ss(XmmRegister dst, CpuRegister src) {
558   EmitOptionalRex32(dst, src);
561   EmitOperand(dst.LowBits(), Operand(src));
565 void X86_64Assembler::cvtsi2sd(XmmRegister dst, CpuRegister src) {
568   EmitOptionalRex32(dst, src);
571   EmitOperand(dst.LowBits(), Operand(src));
575 void X86_64Assembler::cvtss2si(CpuRegister dst, XmmRegister src) {
578   EmitOptionalRex32(dst, src);
581   EmitXmmRegisterOperand(dst.LowBits(), src);
585 void X86_64Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
588   EmitOptionalRex32(dst, src);
591   EmitXmmRegisterOperand(dst.LowBits(), src);
595 void X86_64Assembler::cvtsd2si(CpuRegister dst, XmmRegister src) {
598   EmitOptionalRex32(dst, src);
601   EmitXmmRegisterOperand(dst.LowBits(), src);
605 void X86_64Assembler::cvttss2si(CpuRegister dst, XmmRegister src) {
608   EmitOptionalRex32(dst, src);
611   EmitXmmRegisterOperand(dst.LowBits(), src);
615 void X86_64Assembler::cvttsd2si(CpuRegister dst, XmmRegister src) {
618   EmitOptionalRex32(dst, src);
621   EmitXmmRegisterOperand(dst.LowBits(), src);
625 void X86_64Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
628   EmitOptionalRex32(dst, src);
631   EmitXmmRegisterOperand(dst.LowBits(), src);
635 void X86_64Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
638   EmitOptionalRex32(dst, src);
641   EmitXmmRegisterOperand(dst.LowBits(), src);
664 void X86_64Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
667   EmitOptionalRex32(dst, src);
670   EmitXmmRegisterOperand(dst.LowBits(), src);
674 void X86_64Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
677   EmitOptionalRex32(dst, src);
680   EmitXmmRegisterOperand(dst.LowBits(), src);
684 void X86_64Assembler::xorpd(XmmRegister dst, const Address& src) {
687   EmitOptionalRex32(dst, src);
690   EmitOperand(dst.LowBits(), src);
694 void X86_64Assembler::xorpd(XmmRegister dst, XmmRegister src) {
697   EmitOptionalRex32(dst, src);
700   EmitXmmRegisterOperand(dst.LowBits(), src);
704 void X86_64Assembler::xorps(XmmRegister dst, const Address& src) {
706   EmitOptionalRex32(dst, src);
709   EmitOperand(dst.LowBits(), src);
713 void X86_64Assembler::xorps(XmmRegister dst, XmmRegister src) {
715   EmitOptionalRex32(dst, src);
718   EmitXmmRegisterOperand(dst.LowBits(), src);
722 void X86_64Assembler::andpd(XmmRegister dst, const Address& src) {
725   EmitOptionalRex32(dst, src);
728   EmitOperand(dst.LowBits(), src);
732 void X86_64Assembler::fldl(const Address& src) {
735   EmitOperand(0, src);
753 void X86_64Assembler::fldcw(const Address& src) {
756   EmitOperand(5, src);
774 void X86_64Assembler::fildl(const Address& src) {
777   EmitOperand(5, src);
817 void X86_64Assembler::xchgl(CpuRegister dst, CpuRegister src) {
819   EmitOptionalRex32(dst, src);
821   EmitRegisterOperand(dst.LowBits(), src.LowBits());
825 void X86_64Assembler::xchgq(CpuRegister dst, CpuRegister src) {
827   EmitRex64(dst, src);
829   EmitOperand(dst.LowBits(), Operand(src));
888 void X86_64Assembler::addl(CpuRegister dst, CpuRegister src) {
890   EmitOptionalRex32(dst, src);
892   EmitRegisterOperand(dst.LowBits(), src.LowBits());
961 void X86_64Assembler::andl(CpuRegister dst, CpuRegister src) {
963   EmitOptionalRex32(dst, src);
965   EmitOperand(dst.LowBits(), Operand(src));
984 void X86_64Assembler::orl(CpuRegister dst, CpuRegister src) {
986   EmitOptionalRex32(dst, src);
988   EmitOperand(dst.LowBits(), Operand(src));
999 void X86_64Assembler::xorl(CpuRegister dst, CpuRegister src) {
1001   EmitOptionalRex32(dst, src);
1003   EmitOperand(dst.LowBits(), Operand(src));
1007 void X86_64Assembler::xorq(CpuRegister dst, CpuRegister src) {
1009   EmitRex64(dst, src);
1011   EmitOperand(dst.LowBits(), Operand(src));
1072 void rex_mem_reg(bool force, bool w, Address* mem, Register* src);
1098 void X86_64Assembler::addq(CpuRegister dst, CpuRegister src) {
1101   EmitRex64(src, dst);
1103   EmitRegisterOperand(src.LowBits(), dst.LowBits());
1122 void X86_64Assembler::subl(CpuRegister dst, CpuRegister src) {
1124   EmitOptionalRex32(dst, src);
1126   EmitOperand(dst.LowBits(), Operand(src));
1145 void X86_64Assembler::subq(CpuRegister dst, CpuRegister src) {
1147   EmitRex64(dst, src);
1149   EmitRegisterOperand(dst.LowBits(), src.LowBits());
1183 void X86_64Assembler::imull(CpuRegister dst, CpuRegister src) {
1185   EmitOptionalRex32(dst, src);
1188   EmitOperand(dst.LowBits(), Operand(src));
1642 void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, CpuRegister src) {
1643   EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
1646 void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, XmmRegister src) {
1647   EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
1650 void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, XmmRegister src) {
1651   EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
1654 void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, CpuRegister src) {
1655   EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
1689 void X86_64Assembler::EmitRex64(CpuRegister dst, CpuRegister src) {
1690   EmitOptionalRex(false, true, dst.NeedsRex(), false, src.NeedsRex());
1703 void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src) {
1704   EmitOptionalRex(true, false, dst.NeedsRex(), false, src.NeedsRex());
1807   X86_64ManagedRegister src = msrc.AsX86_64();
1808   if (src.IsNoRegister()) {
1810   } else if (src.IsCpuRegister()) {
1813       movl(Address(CpuRegister(RSP), offs), src.AsCpuRegister());
1816       movq(Address(CpuRegister(RSP), offs), src.AsCpuRegister());
1818   } else if (src.IsRegisterPair()) {
1820     movq(Address(CpuRegister(RSP), offs), src.AsRegisterPairLow());
1822          src.AsRegisterPairHigh());
1823   } else if (src.IsX87Register()) {
1830     CHECK(src.IsXmmRegister());
1832       movss(Address(CpuRegister(RSP), offs), src.AsXmmRegister());
1834       movsd(Address(CpuRegister(RSP), offs), src.AsXmmRegister());
1840   X86_64ManagedRegister src = msrc.AsX86_64();
1841   CHECK(src.IsCpuRegister());
1842   movl(Address(CpuRegister(RSP), dest), src.AsCpuRegister());
1846   X86_64ManagedRegister src = msrc.AsX86_64();
1847   CHECK(src.IsCpuRegister());
1848   movq(Address(CpuRegister(RSP), dest), src.AsCpuRegister());
1874 void X86_64Assembler::StoreSpanning(FrameOffset /*dst*/, ManagedRegister /*src*/,
1879 void X86_64Assembler::Load(ManagedRegister mdest, FrameOffset src, size_t size) {
1886       movl(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
1889       movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
1893     movq(dest.AsRegisterPairLow(), Address(CpuRegister(RSP), src));
1894     movq(dest.AsRegisterPairHigh(), Address(CpuRegister(RSP), FrameOffset(src.Int32Value()+4)));
1897       flds(Address(CpuRegister(RSP), src));
1899       fldl(Address(CpuRegister(RSP), src));
1904       movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), src));
1906       movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), src));
1911 void X86_64Assembler::LoadFromThread64(ManagedRegister mdest, ThreadOffset<8> src, size_t size) {
1917     gs()->movl(dest.AsCpuRegister(), Address::Absolute(src, true));
1920     gs()->movq(dest.AsRegisterPairLow(), Address::Absolute(src, true));
1923       gs()->flds(Address::Absolute(src, true));
1925       gs()->fldl(Address::Absolute(src, true));
1930       gs()->movss(dest.AsXmmRegister(), Address::Absolute(src, true));
1932       gs()->movsd(dest.AsXmmRegister(), Address::Absolute(src, true));
1937 void X86_64Assembler::LoadRef(ManagedRegister mdest, FrameOffset  src) {
1940   movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
1987   X86_64ManagedRegister src = msrc.AsX86_64();
1988   if (!dest.Equals(src)) {
1989     if (dest.IsCpuRegister() && src.IsCpuRegister()) {
1990       movq(dest.AsCpuRegister(), src.AsCpuRegister());
1991     } else if (src.IsX87Register() && dest.IsXmmRegister()) {
1995         CHECK_EQ(src.AsX87Register(), ST0);
1999         CHECK_EQ(src.AsX87Register(), ST0);
2006       UNIMPLEMENTED(FATAL) << ": Move " << dest << ", " << src;
2011 void X86_64Assembler::CopyRef(FrameOffset dest, FrameOffset src,
2015   movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), src));
2037 void X86_64Assembler::Copy(FrameOffset dest, FrameOffset src,
2042     Load(scratch, src, 4);
2044     Load(scratch, FrameOffset(src.Int32Value() + 4), 4);
2047     Load(scratch, src, size);
2057 void X86_64Assembler::Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src,
2061   pushq(Address(CpuRegister(RSP), src));
2075                         ManagedRegister src, Offset src_offset,
2079   pushq(Address(src.AsX86_64().AsCpuRegister(), src_offset));
2083 void X86_64Assembler::Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
2087   CHECK_EQ(dest.Int32Value(), src.Int32Value());
2088   movq(scratch, Address(CpuRegister(RSP), src));
2163 void X86_64Assembler::VerifyObject(ManagedRegister /*src*/, bool /*could_be_null*/) {
2167 void X86_64Assembler::VerifyObject(FrameOffset /*src*/, bool /*could_be_null*/) {