Lines Matching refs:mgr
127 static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
129 return (struct radeon_bomgr *)mgr;
199 static uint64_t radeon_bomgr_find_va(struct radeon_bomgr *mgr, uint64_t size, uint64_t alignment)
204 pipe_mutex_lock(mgr->bo_va_mutex);
206 LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) {
221 pipe_mutex_unlock(mgr->bo_va_mutex);
233 pipe_mutex_unlock(mgr->bo_va_mutex);
238 pipe_mutex_unlock(mgr->bo_va_mutex);
243 offset = mgr->va_offset;
253 list_add(&n->list, &mgr->va_holes);
256 mgr->va_offset += size + waste;
257 pipe_mutex_unlock(mgr->bo_va_mutex);
261 static void radeon_bomgr_force_va(struct radeon_bomgr *mgr, uint64_t va, uint64_t size)
263 pipe_mutex_lock(mgr->bo_va_mutex);
264 if (va >= mgr->va_offset) {
265 if (va > mgr->va_offset) {
269 hole->size = va - mgr->va_offset;
270 hole->offset = mgr->va_offset;
271 list_add(&hole->list, &mgr->va_holes);
274 mgr->va_offset = va + size;
281 LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) {
298 pipe_mutex_unlock(mgr->bo_va_mutex);
301 static void radeon_bomgr_free_va(struct radeon_bomgr *mgr, uint64_t va, uint64_t size)
305 pipe_mutex_lock(mgr->bo_va_mutex);
306 if ((va + size) == mgr->va_offset) {
307 mgr->va_offset = va;
309 if (!LIST_IS_EMPTY(&mgr->va_holes)) {
310 hole = container_of(mgr->va_holes.next, hole, list);
312 mgr->va_offset = hole->offset;
320 hole = container_of(&mgr->va_holes, hole, list);
321 LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) {
327 if (&hole->list != &mgr->va_holes) {
333 if (next != hole && &next->list != &mgr->va_holes &&
344 if (next != hole && &next->list != &mgr->va_holes &&
361 pipe_mutex_unlock(mgr->bo_va_mutex);
367 struct radeon_bomgr *mgr = bo->mgr;
373 pipe_mutex_lock(bo->mgr->bo_handles_mutex);
374 util_hash_table_remove(bo->mgr->bo_handles,
376 pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
386 if (mgr->va) {
387 radeon_bomgr_free_va(mgr, bo->va, bo->va_size);
540 struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
541 struct radeon_drm_winsys *rws = mgr->rws;
575 bo->mgr = mgr;
576 bo->rws = mgr->rws;
581 if (mgr->va) {
585 bo->va = radeon_bomgr_find_va(mgr, bo->va_size, desc->alignment);
604 radeon_bomgr_free_va(mgr, bo->va, bo->va_size);
606 radeon_bomgr_force_va(mgr, bo->va, bo->va_size);
613 static void radeon_bomgr_flush(struct pb_manager *mgr)
637 struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
638 util_hash_table_destroy(mgr->bo_handles);
639 pipe_mutex_destroy(mgr->bo_handles_mutex);
640 pipe_mutex_destroy(mgr->bo_va_mutex);
641 FREE(mgr);
658 struct radeon_bomgr *mgr;
660 mgr = CALLOC_STRUCT(radeon_bomgr);
661 if (!mgr)
664 mgr->base.destroy = radeon_bomgr_destroy;
665 mgr->base.create_buffer = radeon_bomgr_create_bo;
666 mgr->base.flush = radeon_bomgr_flush;
667 mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy;
669 mgr->rws = rws;
670 mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare);
671 pipe_mutex_init(mgr->bo_handles_mutex);
672 pipe_mutex_init(mgr->bo_va_mutex);
674 mgr->va = rws->info.r600_virtual_address;
675 mgr->va_offset = rws->info.r600_va_start;
676 list_inithead(&mgr->va_holes);
678 return &mgr->base;
851 struct radeon_bomgr *mgr = radeon_bomgr(ws->kman);
863 pipe_mutex_lock(mgr->bo_handles_mutex);
866 bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle);
895 bo->mgr = mgr;
896 bo->rws = mgr->rws;
900 util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo);
903 pipe_mutex_unlock(mgr->bo_handles_mutex);
908 if (mgr->va && !bo->va) {
912 bo->va = radeon_bomgr_find_va(mgr, bo->va_size, 1 << 20);
929 radeon_bomgr_free_va(mgr, bo->va, bo->va_size);
931 radeon_bomgr_force_va(mgr, bo->va, bo->va_size);
938 pipe_mutex_unlock(mgr->bo_handles_mutex);