Cross Reference: /external/chromium_org/v8/src/arm64/disasm-arm64.cc

Lines Matching refs:instr
52 void Disassembler::VisitAddSubImmediate(Instruction* instr) {
53   bool rd_is_zr = RdIsZROrSP(instr);
54   bool stack_op = (rd_is_zr || RnIsZROrSP(instr)) &&
55                   (instr->ImmAddSub() == 0) ? true : false;
61   switch (instr->Mask(AddSubImmediateMask)) {
93   Format(instr, mnemonic, form);
97 void Disassembler::VisitAddSubShifted(Instruction* instr) {
98   bool rd_is_zr = RdIsZROrSP(instr);
99   bool rn_is_zr = RnIsZROrSP(instr);
105   switch (instr->Mask(AddSubShiftedMask)) {
140   Format(instr, mnemonic, form);
144 void Disassembler::VisitAddSubExtended(Instruction* instr) {
145   bool rd_is_zr = RdIsZROrSP(instr);
147   Extend mode = static_cast<Extend>(instr->ExtendMode());
153   switch (instr->Mask(AddSubExtendedMask)) {
178   Format(instr, mnemonic, form);
182 void Disassembler::VisitAddSubWithCarry(Instruction* instr) {
183   bool rn_is_zr = RnIsZROrSP(instr);
188   switch (instr->Mask(AddSubWithCarryMask)) {
213   Format(instr, mnemonic, form);
217 void Disassembler::VisitLogicalImmediate(Instruction* instr) {
218   bool rd_is_zr = RdIsZROrSP(instr);
219   bool rn_is_zr = RnIsZROrSP(instr);
223   if (instr->ImmLogical() == 0) {
225     Format(instr, "unallocated", "(LogicalImmediate)");
229   switch (instr->Mask(LogicalImmediateMask)) {
235       unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits
237       if (rn_is_zr && !IsMovzMovnImm(reg_size, instr->ImmLogical())) {
256   Format(instr, mnemonic, form);
289 void Disassembler::VisitLogicalShifted(Instruction* instr) {
290   bool rd_is_zr = RdIsZROrSP(instr);
291   bool rn_is_zr = RnIsZROrSP(instr);
295   switch (instr->Mask(LogicalShiftedMask)) {
318       if (rn_is_zr && (instr->ImmDPShift() == 0) && (instr->ShiftDP() == LSL)) {
336   Format(instr, mnemonic, form);
340 void Disassembler::VisitConditionalCompareRegister(Instruction* instr) {
344   switch (instr->Mask(ConditionalCompareRegisterMask)) {
351   Format(instr, mnemonic, form);
355 void Disassembler::VisitConditionalCompareImmediate(Instruction* instr) {
359   switch (instr->Mask(ConditionalCompareImmediateMask)) {
366   Format(instr, mnemonic, form);
370 void Disassembler::VisitConditionalSelect(Instruction* instr) {
371   bool rnm_is_zr = (RnIsZROrSP(instr) && RmIsZROrSP(instr));
372   bool rn_is_rm = (instr->Rn() == instr->Rm());
378   Condition cond = static_cast<Condition>(instr->Condition());
381   switch (instr->Mask(ConditionalSelectMask)) {
419   Format(instr, mnemonic, form);
423 void Disassembler::VisitBitfield(Instruction* instr) {
424   unsigned s = instr->ImmS();
425   unsigned r = instr->ImmR();
427     ((instr->SixtyFourBits() == 1) ? kXRegSizeInBits : kWRegSizeInBits) - 1;
436   switch (instr->Mask(BitfieldMask)) {
447         } else if ((s == 31) && (instr->SixtyFourBits() == 1)) {
497   Format(instr, mnemonic, form);
501 void Disassembler::VisitExtract(Instruction* instr) {
505   switch (instr->Mask(ExtractMask)) {
508       if (instr->Rn() == instr->Rm()) {
518   Format(instr, mnemonic, form);
522 void Disassembler::VisitPCRelAddressing(Instruction* instr) {
523   switch (instr->Mask(PCRelAddressingMask)) {
524     case ADR: Format(instr, "adr", "'Xd, 'AddrPCRelByte"); break;
526     default: Format(instr, "unimplemented", "(PCRelAddressing)");
531 void Disassembler::VisitConditionalBranch(Instruction* instr) {
532   switch (instr->Mask(ConditionalBranchMask)) {
533     case B_cond: Format(instr, "b.'CBrn", "'BImmCond"); break;
539 void Disassembler::VisitUnconditionalBranchToRegister(Instruction* instr) {
543   switch (instr->Mask(UnconditionalBranchToRegisterMask)) {
548       if (instr->Rn() == kLinkRegCode) {
555   Format(instr, mnemonic, form);
559 void Disassembler::VisitUnconditionalBranch(Instruction* instr) {
563   switch (instr->Mask(UnconditionalBranchMask)) {
568   Format(instr, mnemonic, form);
572 void Disassembler::VisitDataProcessing1Source(Instruction* instr) {
576   switch (instr->Mask(DataProcessing1SourceMask)) {
589   Format(instr, mnemonic, form);
593 void Disassembler::VisitDataProcessing2Source(Instruction* instr) {
597   switch (instr->Mask(DataProcessing2SourceMask)) {
610   Format(instr, mnemonic, form);
614 void Disassembler::VisitDataProcessing3Source(Instruction* instr) {
615   bool ra_is_zr = RaIsZROrSP(instr);
623   switch (instr->Mask(DataProcessing3SourceMask)) {
688   Format(instr, mnemonic, form);
692 void Disassembler::VisitCompareBranch(Instruction* instr) {
696   switch (instr->Mask(CompareBranchMask)) {
703   Format(instr, mnemonic, form);
707 void Disassembler::VisitTestBranch(Instruction* instr) {
715   switch (instr->Mask(TestBranchMask)) {
720   Format(instr, mnemonic, form);
724 void Disassembler::VisitMoveWideImmediate(Instruction* instr) {
731   switch (instr->Mask(MoveWideImmediateMask)) {
740   Format(instr, mnemonic, form);
763 void Disassembler::VisitLoadStorePreIndex(Instruction* instr) {
767   switch (instr->Mask(LoadStorePreIndexMask)) {
773   Format(instr, mnemonic, form);
777 void Disassembler::VisitLoadStorePostIndex(Instruction* instr) {
781   switch (instr->Mask(LoadStorePostIndexMask)) {
787   Format(instr, mnemonic, form);
791 void Disassembler::VisitLoadStoreUnsignedOffset(Instruction* instr) {
795   switch (instr->Mask(LoadStoreUnsignedOffsetMask)) {
802   Format(instr, mnemonic, form);
806 void Disassembler::VisitLoadStoreRegisterOffset(Instruction* instr) {
810   switch (instr->Mask(LoadStoreRegisterOffsetMask)) {
817   Format(instr, mnemonic, form);
821 void Disassembler::VisitLoadStoreUnscaledOffset(Instruction* instr) {
828   switch (instr->Mask(LoadStoreUnscaledOffsetMask)) {
848   Format(instr, mnemonic, form);
852 void Disassembler::VisitLoadLiteral(Instruction* instr) {
856   switch (instr->Mask(LoadLiteralMask)) {
863   Format(instr, mnemonic, form);
878 void Disassembler::VisitLoadStorePairPostIndex(Instruction* instr) {
882   switch (instr->Mask(LoadStorePairPostIndexMask)) {
888   Format(instr, mnemonic, form);
892 void Disassembler::VisitLoadStorePairPreIndex(Instruction* instr) {
896   switch (instr->Mask(LoadStorePairPreIndexMask)) {
902   Format(instr, mnemonic, form);
906 void Disassembler::VisitLoadStorePairOffset(Instruction* instr) {
910   switch (instr->Mask(LoadStorePairOffsetMask)) {
916   Format(instr, mnemonic, form);
920 void Disassembler::VisitLoadStorePairNonTemporal(Instruction* instr) {
924   switch (instr->Mask(LoadStorePairNonTemporalMask)) {
935   Format(instr, mnemonic, form);
939 void Disassembler::VisitFPCompare(Instruction* instr) {
944   switch (instr->Mask(FPCompareMask)) {
951   Format(instr, mnemonic, form);
955 void Disassembler::VisitFPConditionalCompare(Instruction* instr) {
959   switch (instr->Mask(FPConditionalCompareMask)) {
966   Format(instr, mnemonic, form);
970 void Disassembler::VisitFPConditionalSelect(Instruction* instr) {
974   switch (instr->Mask(FPConditionalSelectMask)) {
979   Format(instr, mnemonic, form);
983 void Disassembler::VisitFPDataProcessing1Source(Instruction* instr) {
987   switch (instr->Mask(FPDataProcessing1SourceMask)) {
1007   Format(instr, mnemonic, form);
1011 void Disassembler::VisitFPDataProcessing2Source(Instruction* instr) {
1015   switch (instr->Mask(FPDataProcessing2SourceMask)) {
1031   Format(instr, mnemonic, form);
1035 void Disassembler::VisitFPDataProcessing3Source(Instruction* instr) {
1039   switch (instr->Mask(FPDataProcessing3SourceMask)) {
1050   Format(instr, mnemonic, form);
1054 void Disassembler::VisitFPImmediate(Instruction* instr) {
1058   switch (instr->Mask(FPImmediateMask)) {
1063   Format(instr, mnemonic, form);
1067 void Disassembler::VisitFPIntegerConvert(Instruction* instr) {
1073   switch (instr->Mask(FPIntegerConvertMask)) {
1119   Format(instr, mnemonic, form);
1123 void Disassembler::VisitFPFixedPointConvert(Instruction* instr) {
1128   switch (instr->Mask(FPFixedPointConvertMask)) {
1146   Format(instr, mnemonic, form);
1150 void Disassembler::VisitSystem(Instruction* instr) {
1157   if (instr->Mask(SystemSysRegFMask) == SystemSysRegFixed) {
1158     switch (instr->Mask(SystemSysRegMask)) {
1161         switch (instr->ImmSystemRegister()) {
1170         switch (instr->ImmSystemRegister()) {
1178   } else if (instr->Mask(SystemHintFMask) == SystemHintFixed) {
1179     DCHECK(instr->Mask(SystemHintMask) == HINT);
1180     switch (instr->ImmHint()) {
1187   } else if (instr->Mask(MemBarrierFMask) == MemBarrierFixed) {
1188     switch (instr->Mask(MemBarrierMask)) {
1207   Format(instr, mnemonic, form);
1211 void Disassembler::VisitException(Instruction* instr) {
1215   switch (instr->Mask(ExceptionMask)) {
1226   Format(instr, mnemonic, form);
1230 void Disassembler::VisitUnimplemented(Instruction* instr) {
1231   Format(instr, "unimplemented", "(Unimplemented)");
1235 void Disassembler::VisitUnallocated(Instruction* instr) {
1236   Format(instr, "unallocated", "(Unallocated)");
1240 void Disassembler::ProcessOutput(Instruction* /*instr*/) {
1245 void Disassembler::Format(Instruction* instr, const char* mnemonic,
1247   // TODO(mcapewel) don't think I can use the instr address here - there needs
1251   Substitute(instr, mnemonic);
1254     Substitute(instr, format);
1257   ProcessOutput(instr);
1261 void Disassembler::Substitute(Instruction* instr, const char* string) {
1265       string += SubstituteField(instr, string);
1274 int Disassembler::SubstituteField(Instruction* instr, const char* format) {
1281     case 'D': return SubstituteRegisterField(instr, format);
1282     case 'I': return SubstituteImmediateField(instr, format);
1283     case 'L': return SubstituteLiteralField(instr, format);
1284     case 'H': return SubstituteShiftField(instr, format);
1285     case 'P': return SubstitutePrefetchField(instr, format);
1286     case 'C': return SubstituteConditionField(instr, format);
1287     case 'E': return SubstituteExtendField(instr, format);
1288     case 'A': return SubstitutePCRelAddressField(instr, format);
1289     case 'B': return SubstituteBranchTargetField(instr, format);
1290     case 'O': return SubstituteLSRegOffsetField(instr, format);
1291     case 'M': return SubstituteBarrierField(instr, format);
1300 int Disassembler::SubstituteRegisterField(Instruction* instr,
1305     case 'd': reg_num = instr->Rd(); break;
1306     case 'n': reg_num = instr->Rn(); break;
1307     case 'm': reg_num = instr->Rm(); break;
1308     case 'a': reg_num = instr->Ra(); break;
1311         reg_num = instr->Rt2();
1314         reg_num = instr->Rt();
1329     reg_type = instr->SixtyFourBits() ? 'x' : 'w';
1332     reg_type = ((instr->FPType() & 1) == 0) ? 's' : 'd';
1365 int Disassembler::SubstituteImmediateField(Instruction* instr,
1372         uint64_t imm = instr->ImmMoveWide() << (16 * instr->ShiftMoveWide());
1376         AppendToOutput("#0x%" PRIx64, instr->ImmMoveWide());
1377         if (instr->ShiftMoveWide() > 0) {
1378           AppendToOutput(", lsl #%d", 16 * instr->ShiftMoveWide());
1387                          instr->ImmLLiteral() << kLoadLiteralScaleLog2);
1391           if (instr->ImmLS() != 0) {
1392             AppendToOutput(", #%" PRId64, instr->ImmLS());
1397           if (instr->ImmLSPair() != 0) {
1400             AppendToOutput(", #%" PRId64, instr->ImmLSPair() * scale);
1405           if (instr->ImmLSUnsigned() != 0) {
1407                            instr->ImmLSUnsigned() << instr->SizeLS());
1414       int64_t offset = instr->ImmCondBranch() << 2;
1420       DCHECK(instr->ShiftAddSub() <= 1);
1421       int64_t imm = instr->ImmAddSub() << (12 * instr->ShiftAddSub());
1427         AppendToOutput("#%d", 64 - instr->FPScale());
1430         AppendToOutput("#0x%" PRIx64 " (%.4f)", instr->ImmFP(),
1431                        format[3] == 'S' ? instr->ImmFP32() : instr->ImmFP64());
1436       AppendToOutput("#0x%" PRIx64, instr->ImmLogical());
1440       int nzcv = (instr->Nzcv() << Flags_offset);
1448       AppendToOutput("#%d", instr->ImmCondCmp());
1452       return SubstituteBitfieldImmediateField(instr, format);
1455       AppendToOutput("#%d", instr->ImmS());
1459       AppendToOutput("#%d", (instr->ImmTestBranchBit5() << 5) |
1460                             instr->ImmTestBranchBit40());
1464       AppendToOutput("#0x%x", instr->ImmException());
1475 int Disassembler::SubstituteBitfieldImmediateField(Instruction* instr,
1478   unsigned r = instr->ImmR();
1479   unsigned s = instr->ImmS();
1498       unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits
1511 int Disassembler::SubstituteLiteralField(Instruction* instr,
1516   switch (instr->Mask(LoadLiteralMask)) {
1521       AppendToOutput("(addr 0x%016" PRIxPTR ")", instr->LiteralAddress());
1530 int Disassembler::SubstituteShiftField(Instruction* instr, const char* format) {
1532   DCHECK(instr->ShiftDP() <= 0x3);
1536       DCHECK(instr->ShiftDP() != ROR);
1539       if (instr->ImmDPShift() != 0) {
1541         AppendToOutput(", %s #%" PRId64, shift_type[instr->ShiftDP()],
1542                        instr->ImmDPShift());
1553 int Disassembler::SubstituteConditionField(Instruction* instr,
1562     case 'B': cond = instr->ConditionBranch(); break;
1564       cond = NegateCondition(static_cast<Condition>(instr->Condition()));
1567     default: cond = instr->Condition();
1574 int Disassembler::SubstitutePCRelAddressField(Instruction* instr,
1579   int offset = instr->ImmPCRel();
1590                  instr->InstructionAtOffset(offset, Instruction::NO_CHECK));
1595 int Disassembler::SubstituteBranchTargetField(Instruction* instr,
1602     case 'n': offset = instr->ImmUncondBranch(); break;
1604     case 'o': offset = instr->ImmCondBranch(); break;
1606     case 'm': offset = instr->ImmCmpBranch(); break;
1608     case 'e': offset = instr->ImmTestBranch(); break;
1617                  instr->InstructionAtOffset(offset), Instruction::NO_CHECK);
1622 int Disassembler::SubstituteExtendField(Instruction* instr,
1625   DCHECK(instr->ExtendMode() <= 7);
1633   if (((instr->Rd() == kZeroRegCode) || (instr->Rn() == kZeroRegCode)) &&
1634       (((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) ||
1635        (instr->ExtendMode() == UXTX))) {
1636     if (instr->ImmExtendShift() > 0) {
1637       AppendToOutput(", lsl #%d", instr->ImmExtendShift());
1640     AppendToOutput(", %s", extend_mode[instr->ExtendMode()]);
1641     if (instr->ImmExtendShift() > 0) {
1642       AppendToOutput(" #%d", instr->ImmExtendShift());
1649 int Disassembler::SubstituteLSRegOffsetField(Instruction* instr,
1656   unsigned shift = instr->ImmShiftLS();
1657   Extend ext = static_cast<Extend>(instr->ExtendMode());
1660   unsigned rm = instr->Rm();
1671       AppendToOutput(" #%d", instr->SizeLS());
1678 int Disassembler::SubstitutePrefetchField(Instruction* instr,
1683   int prefetch_mode = instr->PrefetchMode();
1693 int Disassembler::SubstituteBarrierField(Instruction* instr,
1704   int domain = instr->ImmBarrierDomain();
1705   int type = instr->ImmBarrierType();
1726 void PrintDisassembler::ProcessOutput(Instruction* instr) {
1728           reinterpret_cast<uint64_t>(instr), instr->InstructionBits(),
1790   virtual void ProcessOutput(v8::internal::Instruction* instr) {
1806                                     byte* instr) {
1811   decoder.Decode(reinterpret_cast<v8::internal::Instruction*>(instr));
1816 int Disassembler::ConstantPoolSizeAt(byte* instr) {
1818       reinterpret_cast<v8::internal::Instruction*>(instr));