Lines Matching refs:operand
57 const Operand& operand,
61 if (operand.NeedsRelocation(this)) {
63 Ldr(temp, operand.immediate());
66 } else if (operand.IsImmediate()) {
67 int64_t immediate = operand.ImmediateValue();
141 } else if (operand.IsExtendedRegister()) {
142 DCHECK(operand.reg().SizeInBits() <= rd.SizeInBits());
145 DCHECK(operand.shift_amount() <= 4);
146 DCHECK(operand.reg().Is64Bits() ||
147 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
149 EmitExtendShift(temp, operand.reg(), operand.extend(),
150 operand.shift_amount());
154 // The operand can be encoded in the instruction.
155 DCHECK(operand.IsShiftedRegister());
156 Logical(rd, rn, operand, op);
241 const Operand& operand,
251 if (operand.NeedsRelocation(this)) {
252 Ldr(dst, operand.immediate());
254 } else if (operand.IsImmediate()) {
256 Mov(dst, operand.ImmediateValue());
258 } else if (operand.IsShiftedRegister() && (operand.shift_amount() != 0)) {
262 EmitShift(dst, operand.reg(), operand.shift(), operand.shift_amount());
264 } else if (operand.IsExtendedRegister()) {
267 EmitExtendShift(dst, operand.reg(), operand.extend(),
268 operand.shift_amount());
279 // If csp is an operand, add #0 is emitted, otherwise, orr #0.
280 if (!rd.Is(operand.reg()) || (rd.Is32Bits() &&
282 Assembler::mov(rd, operand.reg());
296 void MacroAssembler::Mvn(const Register& rd, const Operand& operand) {
299 if (operand.NeedsRelocation(this)) {
300 Ldr(rd, operand.immediate());
303 } else if (operand.IsImmediate()) {
305 Mov(rd, ~operand.ImmediateValue());
307 } else if (operand.IsExtendedRegister()) {
310 EmitExtendShift(rd, operand.reg(), operand.extend(),
311 operand.shift_amount());
315 mvn(rd, operand);
349 const Operand& operand,
354 if (operand.NeedsRelocation(this)) {
357 Ldr(temp, operand.immediate());
360 } else if ((operand.IsShiftedRegister() && (operand.shift_amount() == 0)) ||
361 (operand.IsImmediate() &&
362 IsImmConditionalCompare(operand.ImmediateValue()))) {
363 // The immediate can be encoded in the instruction, or the operand is an
365 ConditionalCompare(rn, operand, nzcv, cond, op);
368 // The operand isn't directly supported by the instruction: perform the
372 Mov(temp, operand);
380 const Operand& operand,
385 if (operand.IsImmediate()) {
388 int64_t imm = operand.ImmediateValue();
402 } else if (operand.IsShiftedRegister() && (operand.shift_amount() == 0)) {
404 csel(rd, rn, operand.reg(), cond);
409 Mov(temp, operand);
460 // return a new leftward-shifting operand.
464 // return a new rightward-shifting operand.
477 const Operand& operand,
480 if (operand.IsZero() && rd.Is(rn) && rd.Is64Bits() && rn.Is64Bits() &&
481 !operand.NeedsRelocation(this) && (S == LeaveFlags)) {
486 if (operand.NeedsRelocation(this)) {
489 Ldr(temp, operand.immediate());
491 } else if ((operand.IsImmediate() &&
492 !IsImmAddSub(operand.ImmediateValue())) ||
493 (rn.IsZero() && !operand.IsShiftedRegister()) ||
494 (operand.IsShiftedRegister() && (operand.shift() == ROR))) {
497 if (operand.IsImmediate()) {
499 MoveImmediateForShiftedOp(temp, operand.ImmediateValue());
502 Mov(temp, operand);
506 AddSub(rd, rn, operand, S, op);
513 const Operand& operand,
519 if (operand.NeedsRelocation(this)) {
521 Ldr(temp, operand.immediate());
524 } else if (operand.IsImmediate() ||
525 (operand.IsShiftedRegister() && (operand.shift() == ROR))) {
528 Mov(temp, operand);
531 } else if (operand.IsShiftedRegister() && (operand.shift_amount() != 0)) {
533 DCHECK(operand.reg().SizeInBits() == rd.SizeInBits());
534 DCHECK(operand.shift() != ROR);
535 DCHECK(is_uintn(operand.shift_amount(),
539 EmitShift(temp, operand.reg(), operand.shift(), operand.shift_amount());
542 } else if (operand.IsExtendedRegister()) {
544 DCHECK(operand.reg().SizeInBits() <= rd.SizeInBits());
547 DCHECK(operand.shift_amount() <= 4);
548 DCHECK(operand.reg().Is64Bits() ||
549 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
551 EmitExtendShift(temp, operand.reg(), operand.extend(),
552 operand.shift_amount());
557 AddSubWithCarry(rd, rn, operand, S, op);