Cross Reference: /external/chromium_org/v8/src/mips/assembler-mips.cc

Lines Matching refs:SPECIAL
23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
539       (opcode == SPECIAL && rt_field == 0 &&
558     return GetOpcodeField(instr) == SPECIAL && GetFunctionField(instr) == JR;
560     return GetOpcodeField(instr) == SPECIAL &&
567   return GetOpcodeField(instr) == SPECIAL &&
601   bool ret = (opcode == SPECIAL && function == SLL &&
1411     GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR);
1435   GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR);
1471   GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU);
1481   GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU);
1489     GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH);
1496   GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH_U);
1502   GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH);
1508   GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH_U);
1514   GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD);
1520   GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD_U);
1525   GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULT);
1530   GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULTU);
1535   GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIV);
1541   GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD);
1546   GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU);
1552   GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U);
1559   GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND);
1570   GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR);
1581   GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR);
1592   GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR);
1606   GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL);
1611   GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV);
1616   GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRL);
1621   GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV);
1626   GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRA);
1631   GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV);
1639   Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift)
1649   Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift)
1794   Instr break_instr = SPECIAL | BREAK | (code << 6);
1816   Instr instr = SPECIAL | TGE | rs.code() << kRsShift
1824   Instr instr = SPECIAL | TGEU | rs.code() << kRsShift
1833       SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
1841       SPECIAL | TLTU | rs.code() << kRsShift
1850       SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
1858       SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
1866   GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI);
1871   GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO);
1877   GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT);
1882   GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU);
1898   GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ);
1903   GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN);
1910   GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
1917   GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
1927     GenInstrRegister(SPECIAL, rs, zero_reg, rd, 1, CLZ_R6);
2668       *(p+2) = SPECIAL | rs_field | rd_field | JALR;
2680         *(p + 2) = SPECIAL | rs_field | (zero_reg.code() << kRdShift) | JALR;
2682         *(p + 2) = SPECIAL | rs_field | JR;
2711     *(p + 2) = SPECIAL | rs_field | rd_field | JALR;
2719       *(p + 2) = SPECIAL | rs_field | (zero_reg.code() << kRdShift) | JALR;
2721       *(p + 2) = SPECIAL | rs_field | JR;