Lines Matching refs:destination
49 // the same as the destination, the destination is ignored and
71 // Clear this move's destination to indicate a pending move. The actual
72 // destination is saved in a stack-allocated local. Recursion may allow
75 LOperand* destination = moves_[index].destination();
80 // as this one's destination blocks this one so recursively perform all
84 if (other_move.Blocks(destination) && !other_move.IsPending()) {
90 // not be swapped). Since this move's destination is B and there is
99 // pending, so restore its destination.
100 moves_[index].set_destination(destination);
104 if (moves_[index].source()->Equals(destination)) {
114 if (other_move.Blocks(destination)) {
128 // No operand should be the destination for more than one move.
130 LOperand* destination = moves_[i].destination();
132 SLOW_DCHECK(!destination->Equals(moves_[j].destination()));
144 LOperand* destination = moves_[index].destination();
146 // Dispatch on the source and destination operand kinds. Not all
150 if (destination->IsRegister()) {
151 Register dst = cgen_->ToRegister(destination);
154 DCHECK(destination->IsStackSlot());
155 Operand dst = cgen_->ToOperand(destination);
161 if (destination->IsRegister()) {
162 Register dst = cgen_->ToRegister(destination);
165 DCHECK(destination->IsStackSlot());
166 Operand dst = cgen_->ToOperand(destination);
173 if (destination->IsRegister()) {
174 Register dst = cgen_->ToRegister(destination);
189 } else if (destination->IsDoubleRegister()) {
192 XMMRegister dst = cgen_->ToDoubleRegister(destination);
200 DCHECK(destination->IsStackSlot());
201 Operand dst = cgen_->ToOperand(destination);
215 if (destination->IsDoubleRegister()) {
216 __ movaps(cgen_->ToDoubleRegister(destination), src);
218 DCHECK(destination->IsDoubleStackSlot());
219 __ movsd(cgen_->ToOperand(destination), src);
223 if (destination->IsDoubleRegister()) {
224 __ movsd(cgen_->ToDoubleRegister(destination), src);
226 DCHECK(destination->IsDoubleStackSlot());
228 __ movsd(cgen_->ToOperand(destination), xmm0);
240 LOperand* destination = moves_[index].destination();
242 // Dispatch on the source and destination operand kinds. Not all
244 if (source->IsRegister() && destination->IsRegister()) {
247 Register dst = cgen_->ToRegister(destination);
250 } else if ((source->IsRegister() && destination->IsStackSlot()) ||
251 (source->IsStackSlot() && destination->IsRegister())) {
254 cgen_->ToRegister(source->IsRegister() ? source : destination);
256 cgen_->ToOperand(source->IsRegister() ? destination : source);
261 } else if ((source->IsStackSlot() && destination->IsStackSlot()) ||
262 (source->IsDoubleStackSlot() && destination->IsDoubleStackSlot())) {
265 Operand dst = cgen_->ToOperand(destination);
271 } else if (source->IsDoubleRegister() && destination->IsDoubleRegister()) {
274 XMMRegister destination_reg = cgen_->ToDoubleRegister(destination);
279 } else if (source->IsDoubleRegister() || destination->IsDoubleRegister()) {
281 DCHECK((source->IsDoubleRegister() && destination->IsDoubleStackSlot()) ||
282 (source->IsDoubleStackSlot() && destination->IsDoubleRegister()));
285 : destination);
286 LOperand* other = source->IsDoubleRegister() ? destination : source;
298 // The swap of source and destination has executed a move from source to
299 // destination.
303 // this move's source or destination needs to have their source
308 moves_[i].set_source(destination);
309 } else if (other_move.Blocks(destination)) {