Lines Matching refs:x12
106 // stmfd sp!, {x4-x12, x14} //stack stores the values of the arguments
132 sub x12,x0,#2 //pu1_src - 2
134 add x4,x12,x2 //pu1_src_tmp2_8 = pu1_src + src_strd
174 add x4,x12,x2
177 and x0, x12, #31
178 add x20,x12, x2 , lsl #1
186 add x19,x12,#8
187 ld1 { v0.2s},[x12],x11 //vector load pu1_src
191 ld1 { v2.2s},[x12],x11 //vector load pu1_src
196 ld1 { v4.2s},[x12],x11 //vector load pu1_src
201 ld1 { v6.2s},[x12],x9 //vector load pu1_src
242 // and x7, x12, #31 //decrement the wd loop
244 add x20,x12, x2 , lsl #2
256 // add x20,x12,x2,lsl #1
257 //csel x12, x20, x12,eq
258 // sub x20,x12,x5
259 //csel x12, x20, x12,eq
260 add x20,x12,x7
261 csel x12, x20, x12,eq
262 add x20,x12,x2
272 add x19,x12,#8
273 ld1 { v0.2s},[x12],x11 //vector load pu1_src
280 ld1 { v2.2s},[x12],x11 //vector load pu1_src
285 ld1 { v4.2s},[x12],x11 //vector load pu1_src
292 ld1 { v6.2s},[x12],x9 //vector load pu1_src
355 // add x20,x12,x2,lsl #1
356 //csel x12, x20, x12,eq
357 add x20,x12,x7
358 csel x12, x20, x12,eq
360 // sub x20,x12,x5
361 //csel x12, x20, x12,eq
363 add x20,x12,x2
367 add x19,x12,#8
368 ld1 { v0.2s},[x12],x11 //vector load pu1_src
373 ld1 { v2.2s},[x12],x11 //vector load pu1_src
378 ld1 { v4.2s},[x12],x11 //vector load pu1_src
382 ld1 { v6.2s},[x12],x9 //vector load pu1_src
439 add x20,x12,x2,lsl #1
440 csel x12, x20, x12,ne
441 sub x20,x12,x5
442 csel x12, x20, x12,ne
458 add x4,x12,x2 //pu1_src + src_strd
461 //ld1 {v0.2s, v1.2s},[x12],x11 //vector load pu1_src
462 ld1 {v0.2s},[x12],x11 //vector load pu1_src
463 ld1 {v1.2s},[x12],x11 //vector load pu1_src
464 ld1 {v2.2s},[x12],x11 //vector load pu1_src
465 ld1 {v3.2s},[x12],x11 //vector load pu1_src
495 sub x12,x12,x5
498 add x12,x12,x2,lsl #1
520 mov x12,x9
525 ld1 {v0.2s},[x12],x11 //(1)vector load pu1_src
526 ld1 {v1.2s},[x12],x11 //(1)vector load pu1_src
527 ld1 {v2.2s},[x12],x11 //(1)vector load pu1_src
528 ld1 {v3.2s},[x12],x0 //(1)vector load pu1_src
530 ld1 {v4.2s},[x12],x11 //(2)vector load pu1_src
531 ld1 {v5.2s},[x12],x11 //(2)vector load pu1_src
532 ld1 {v6.2s},[x12],x11 //(2)vector load pu1_src
533 ld1 {v7.2s},[x12],x0 //(2)vector load pu1_src
535 ld1 {v14.2s},[x12],x11 //(3)vector load pu1_src
538 ld1 {v15.2s},[x12],x11 //(3)vector load pu1_src
541 ld1 {v16.2s},[x12],x11 //(3)vector load pu1_src
544 ld1 {v17.2s},[x12],x0 //(3)vector load pu1_src
547 ld1 {v18.2s},[x12],x11 //(4)vector load pu1_src
550 ld1 {v19.2s},[x12],x11 //(4)vector load pu1_src
553 ld1 {v20.2s},[x12],x11 //(4)vector load pu1_src
556 ld1 {v21.2s},[x12],x2 //(4)vector load pu1_src
566 mov x12,x9
568 ld1 {v0.2s},[x12],x11 //(1_1)vector load pu1_src
571 ld1 {v1.2s},[x12],x11 //(1_1)vector load pu1_src
574 ld1 {v2.2s},[x12],x11 //(1_1)vector load pu1_src
577 ld1 {v3.2s},[x12],x0 //(1_1)vector load pu1_src
583 ld1 {v4.2s},[x12],x11 //(2_1)vector load pu1_src
586 ld1 {v5.2s},[x12],x11 //(2_1)vector load pu1_src
589 ld1 {v6.2s},[x12],x11 //(2_1)vector load pu1_src
592 ld1 {v7.2s},[x12],x0 //(2_1)vector load pu1_src
598 ld1 {v14.2s},[x12],x11 //(3_1)vector load pu1_src
601 ld1 {v15.2s},[x12],x11 //(3_1)vector load pu1_src
604 ld1 {v16.2s},[x12],x11 //(3_1)vector load pu1_src
607 ld1 {v17.2s},[x12],x0 //(3_1)vector load pu1_src
614 ld1 {v18.2s},[x12],x11 //(4_1)vector load pu1_src
616 ld1 {v19.2s},[x12],x11 //(4_1)vector load pu1_src
619 ld1 {v20.2s},[x12],x11 //(4_1)vector load pu1_src
624 ld1 {v21.2s},[x12],x0 //(4_1)vector load pu1_src
666 csel x12, x9, x12,gt
675 add x4,x12,x2 //pu1_src + src_strd
678 //ld1 {v0.2s, v1.2s},[x12] //vector load pu1_src
679 ld1 {v20.2s},[x12],x11 //vector load pu1_src
680 ld1 {v21.2s},[x12],x11 //vector load pu1_src
681 ld1 {v22.2s},[x12],x11 //vector load pu1_src
682 ld1 {v23.2s},[x12] //vector load pu1_src
685 //add x12,x12,#4 //increment the input pointer
688 sub x12,x12,#2 //increment the input pointer
738 sub x12,x12,x5
741 add x12,x12,x2,lsl #1
755 //ld1 {v0.2s, v1.2s},[x12] //vector load pu1_src
756 ld1 {v20.2s},[x12],x11 //vector load pu1_src
757 ld1 {v21.2s},[x12],x11 //vector load pu1_src
758 ld1 {v22.2s},[x12],x11 //vector load pu1_src
759 ld1 {v23.2s},[x12] //vector load pu1_src
764 //add x12,x12,#4 //pu1_src + 4
765 sub x12, x12, #2
785 //add x12,x12,x9 //pu1_src + src_strd
792 // ldmfd sp!,{x4-x12,x15} //reload the registers from sp