Lines Matching refs:DestReg
1267 static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg,
1271 return ((DestReg - SrcReg) & 0x1f) < NumRegs;
1276 unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode,
1281 uint16_t DestEncoding = TRI->getEncodingValue(DestReg);
1294 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI);
1302 unsigned DestReg, unsigned SrcReg,
1304 if (AArch64::GPR32spRegClass.contains(DestReg) &&
1308 if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
1312 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32,
1326 BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg)
1332 BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg).addImm(0).addImm(
1337 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32,
1351 BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg)
1359 if (AArch64::GPR64spRegClass.contains(DestReg) &&
1361 if (DestReg == AArch64::SP || SrcReg == AArch64::SP) {
1363 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg)
1368 BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg).addImm(0).addImm(
1372 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg)
1380 if (AArch64::DDDDRegClass.contains(DestReg) &&
1384 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1390 if (AArch64::DDDRegClass.contains(DestReg) &&
1394 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1400 if (AArch64::DDRegClass.contains(DestReg) &&
1403 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1409 if (AArch64::QQQQRegClass.contains(DestReg) &&
1413 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1419 if (AArch64::QQQRegClass.contains(DestReg) &&
1423 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1429 if (AArch64::QQRegClass.contains(DestReg) &&
1432 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1437 if (AArch64::FPR128RegClass.contains(DestReg) &&
1440 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1451 .addReg(DestReg, RegState::Define)
1458 if (AArch64::FPR64RegClass.contains(DestReg) &&
1461 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::dsub,
1465 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1469 BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestReg)
1475 if (AArch64::FPR32RegClass.contains(DestReg) &&
1478 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::ssub,
1482 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1486 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1492 if (AArch64::FPR16RegClass.contains(DestReg) &&
1495 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
1499 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1503 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
1507 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1513 if (AArch64::FPR8RegClass.contains(DestReg) &&
1516 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
1520 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1524 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
1528 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1535 if (AArch64::FPR64RegClass.contains(DestReg) &&
1537 BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestReg)
1541 if (AArch64::GPR64RegClass.contains(DestReg) &&
1543 BuildMI(MBB, I, DL, get(AArch64::FMOVDXr), DestReg)
1548 if (AArch64::FPR32RegClass.contains(DestReg) &&
1550 BuildMI(MBB, I, DL, get(AArch64::FMOVWSr), DestReg)
1554 if (AArch64::GPR32RegClass.contains(DestReg) &&
1556 BuildMI(MBB, I, DL, get(AArch64::FMOVSWr), DestReg)
1561 if (DestReg == AArch64::NZCV) {
1571 assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy");
1573 .addReg(DestReg)
1681 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
1708 if (TargetRegisterInfo::isVirtualRegister(DestReg))
1709 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass);
1711 assert(DestReg != AArch64::WSP);
1718 if (TargetRegisterInfo::isVirtualRegister(DestReg))
1719 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass);
1721 assert(DestReg != AArch64::SP);
1770 .addReg(DestReg, getDefRegState(true))
1779 unsigned DestReg, unsigned SrcReg, int Offset,
1782 if (DestReg == SrcReg && Offset == 0)
1790 // scratch register. If DestReg is a virtual register, use it as the
1793 // slightly if DestReg is SP which is always 16-byte aligned, so the scratch
1817 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
1823 SrcReg = DestReg;
1828 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)