Lines Matching refs:AddDefaultPred

6335     AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6341 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6348 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
6362 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
6371 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
6375 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
6380 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
6383 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
6394 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
6399 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
6402 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
6522 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
6528 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
6533 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
6539 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
6544 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
6555 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
6561 AddDefaultPred(
6574 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
6580 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
6595 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
6598 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
6609 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
6615 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
6620 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
6630 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
6638 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
6650 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
6656 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
6661 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
6667 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
6672 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6687 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
6691 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6703 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
6707 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
6715 AddDefaultPred(
6870 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
6875 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
6881 AddDefaultPred(MIB);
6883 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
6887 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
6902 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
6906 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc)).addReg(Data)
6912 AddDefaultPred(MIB);
6914 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
6917 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7055 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), Vtmp)
7059 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
7073 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci)).addReg(
7076 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp)).addReg(
7118 AddDefaultPred(MIB);
7123 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
7217 AddDefaultCC(AddDefaultPred(BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr),
7356 AddDefaultPred(BuildMI(BB, dl,
7365 AddDefaultPred(BuildMI(BB, dl,
7381 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
7442 AddDefaultPred(BuildMI(BB, dl,