Cross Reference: /external/llvm/lib/Target/ARM/MLxExpansionPass.cpp

Lines Matching refs:MI
62     void pushStack(MachineInstr *MI);
63     MachineInstr *getAccDefMI(MachineInstr *MI) const;
64     unsigned getDefReg(MachineInstr *MI) const;
65     bool hasLoopHazard(MachineInstr *MI) const;
66     bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
67     bool FindMLxHazard(MachineInstr *MI);
68     void ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI,
81 void MLxExpansion::pushStack(MachineInstr *MI) {
82   LastMIs[MIIdx] = MI;
87 MachineInstr *MLxExpansion::getAccDefMI(MachineInstr *MI) const {
89   // real definition MI. This is important for _sfp instructions.
90   unsigned Reg = MI->getOperand(1).getReg();
94   MachineBasicBlock *MBB = MI->getParent();
117 unsigned MLxExpansion::getDefReg(MachineInstr *MI) const {
118   unsigned Reg = MI->getOperand(0).getReg();
123   MachineBasicBlock *MBB = MI->getParent();
143 bool MLxExpansion::hasLoopHazard(MachineInstr *MI) const {
144   unsigned Reg = MI->getOperand(1).getReg();
148   MachineBasicBlock *MBB = MI->getParent();
182   return DefMI == MI;
185 bool MLxExpansion::hasRAWHazard(unsigned Reg, MachineInstr *MI) const {
187   const MCInstrDesc &MCID = MI->getDesc();
189   if (MI->mayStore())
195     return MI->readsRegister(Reg, TRI);
213 bool MLxExpansion::FindMLxHazard(MachineInstr *MI) {
220   MachineInstr *DefMI = getAccDefMI(MI);
238     return isFpMulInstruction(DefMI->getOpcode()) || hasLoopHazard(MI);
240   if (IgnoreStall.count(MI))
262     if (i <= Limit2 && hasRAWHazard(getDefReg(MI), NextMI))
272 MLxExpansion::ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI,
275   unsigned DstReg = MI->getOperand(0).getReg();
276   bool DstDead = MI->getOperand(0).isDead();
277   unsigned AccReg = MI->getOperand(1).getReg();
278   unsigned Src1Reg = MI->getOperand(2).getReg();
279   unsigned Src2Reg = MI->getOperand(3).getReg();
280   bool Src1Kill = MI->getOperand(2).isKill();
281   bool Src2Kill = MI->getOperand(3).isKill();
282   unsigned LaneImm = HasLane ? MI->getOperand(4).getImm() : 0;
284   ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm();
285   unsigned PredReg = MI->getOperand(++NextOp).getReg();
289   const MachineFunction &MF = *MI->getParent()->getParent();
293   MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
300   MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
313       dbgs() << "Expanding: " << *MI;
315       MachineBasicBlock::iterator MII = MI;
324   MI->eraseFromParent();
337     MachineInstr *MI = &*MII;
339     if (MI->isPosition() || MI->isImplicitDef() || MI->isCopy()) {
344     const MCInstrDesc &MCID = MI->getDesc();
345     if (MI->isBarrier()) {
364           !FindMLxHazard(MI))
365         pushStack(MI);
367         ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane);
368         E = MBB.rend(); // May have changed if MI was the 1st instruction.