Lines Matching refs:DestReg

65                                       unsigned DestReg, unsigned SubIdx,
77 .addReg(DestReg, getDefRegState(true), SubIdx)
91 unsigned DestReg, unsigned BaseReg,
97 bool isHigh = !isARMLowRegister(DestReg) ||
108 unsigned LdReg = DestReg;
109 if (DestReg == ARM::SP) {
129 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
132 if (DestReg == ARM::SP || isSub)
168 unsigned DestReg, unsigned BaseReg,
184 if (DestReg == BaseReg && BaseReg == ARM::SP) {
206 if (DestReg != BaseReg)
209 if (DestReg == ARM::SP) {
223 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
228 DestReg, BaseReg, NumBytes, true,
234 if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
235 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
241 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)
245 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
249 BaseReg = DestReg;
259 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
262 MIB.addReg(DestReg).addImm(ThisVal);
267 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
274 BaseReg = DestReg;
290 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
291 .addReg(DestReg, RegState::Kill)
301 unsigned DestReg, int Imm,
312 DestReg))
315 emitThumbRegPlusImmediate(MBB, MBBI, dl, DestReg, DestReg, Imm, TII, MRI);
318 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
319 .addReg(DestReg, RegState::Kill));
397 unsigned DestReg = MI.getOperand(0).getReg();
403 emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII,
423 emitThumbRegPlusImmediate(MBB, NII, dl, DestReg, DestReg, Offset, TII,
429 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
432 MI.getOperand(FrameRegIdx).ChangeToRegister(DestReg, false, false, true);