Lines Matching refs:DestReg
84 unsigned DestReg, unsigned SrcReg,
89 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
110 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
118 if (Mips::CCRRegClass.contains(DestReg))
120 else if (Mips::FGR32RegClass.contains(DestReg))
122 else if (Mips::HI32RegClass.contains(DestReg))
123 Opc = Mips::MTHI, DestReg = 0;
124 else if (Mips::LO32RegClass.contains(DestReg))
125 Opc = Mips::MTLO, DestReg = 0;
126 else if (Mips::HI32DSPRegClass.contains(DestReg))
128 else if (Mips::LO32DSPRegClass.contains(DestReg))
130 else if (Mips::DSPCCRegClass.contains(DestReg)) {
133 .addReg(DestReg, RegState::ImplicitDefine);
136 else if (Mips::MSACtrlRegClass.contains(DestReg))
139 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
141 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
143 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
145 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
156 if (Mips::HI64RegClass.contains(DestReg))
157 Opc = Mips::MTHI64, DestReg = 0;
158 else if (Mips::LO64RegClass.contains(DestReg))
159 Opc = Mips::MTLO64, DestReg = 0;
160 else if (Mips::FGR64RegClass.contains(DestReg))
163 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
172 if (DestReg)
173 MIB.addReg(DestReg, RegState::Define);
227 unsigned DestReg, int FI, const TargetRegisterClass *RC,
262 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)