Cross Reference: /external/llvm/lib/Target/R600/AMDGPUInstrInfo.cpp

Lines Matching defs:AMDGPUInstrInfo
1 //===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===//
16 #include "AMDGPUInstrInfo.h"
31 void AMDGPUInstrInfo::anchor() {}
33 AMDGPUInstrInfo::AMDGPUInstrInfo(const AMDGPUSubtarget &st)
36 const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const {
40 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
47 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
53 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
59 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
65 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI,
70 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI,
75 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI,
83 AMDGPUInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
89 bool AMDGPUInstrInfo::getNextBranchInstr(MachineBasicBlock::iterator &iter,
106 AMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
116 AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
124 bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const {
173 AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
181 AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
189 AMDGPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
195 AMDGPUInstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
204 AMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
211 AMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
218 bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
230 AMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
235 void AMDGPUInstrInfo::insertNoop(MachineBasicBlock &MBB,
240 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const {
245 AMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
252 bool AMDGPUInstrInfo::DefinesPredicate(MachineInstr *MI,
258 bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const {
264 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
269 bool AMDGPUInstrInfo::isRegisterStore(const MachineInstr &MI) const {
273 bool AMDGPUInstrInfo::isRegisterLoad(const MachineInstr &MI) const {
277 int AMDGPUInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
312 int AMDGPUInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
328 int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {