Cross Reference: /external/llvm/lib/Target/R600/SIFixSGPRCopies.cpp

Lines Matching refs:MRI
88                                            const MachineRegisterInfo &MRI,
92                                                  const MachineRegisterInfo &MRI,
96                         const MachineRegisterInfo &MRI) const;
118   const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
124     if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg())))
135                                                  const MachineRegisterInfo &MRI,
143   const TargetRegisterClass *RC = MRI.getRegClass(Reg);
146        I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) {
149       RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI,
161                                                  const MachineRegisterInfo &MRI,
168   MachineInstr *Def = MRI.getVRegDef(Reg);
170     return TRI->getSubRegClass(MRI.getRegClass(Reg), SubReg);
173   return inferRegClassFromDef(TRI, MRI, Def->getOperand(1).getReg(),
179                                       const MachineRegisterInfo &MRI) const {
184   const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
189       MRI.getRegClass(SrcReg) == &AMDGPU::VReg_1RegClass)
192   SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg);
197   MachineRegisterInfo &MRI = MF.getRegInfo();
209       if (MI.getOpcode() == AMDGPU::COPY && isVGPRToSGPRCopy(MI, TRI, MRI)) {
224           const TargetRegisterClass *RC = inferRegClassFromDef(TRI, MRI, Reg,
226           MRI.constrainRegClass(Reg, RC);
229         const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg,
232           MRI.constrainRegClass(Reg, &AMDGPU::VReg_32RegClass);
235         if (!TRI->isSGPRClass(MRI.getRegClass(Reg)))
242           if (TRI->hasVGPRs(MRI.getRegClass(Reg))) {
263         DstRC = MRI.getRegClass(MI.getOperand(0).getReg());
264         Src0RC = MRI.getRegClass(MI.getOperand(1).getReg());
265         Src1RC = MRI.getRegClass(MI.getOperand(2).getReg());