Lines Matching refs:Dst
200 unsigned Dst = MI.getOperand(0).getReg();
204 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
209 .addReg(Dst);
220 unsigned Dst = MI.getOperand(0).getReg();
223 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
234 unsigned Dst = MI.getOperand(0).getReg();
238 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
249 unsigned Dst = MI.getOperand(0).getReg();
253 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
404 unsigned Dst = MI.getOperand(0).getReg();
412 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
425 unsigned Dst = MI.getOperand(0).getReg();
428 unsigned SubReg = TRI->getSubReg(Dst, AMDGPU::sub0);
430 SubReg = Dst;
437 .addReg(Dst, RegState::Implicit);