Lines Matching refs:X86
1 //===-- X86AsmInstrumentation.cpp - Instrument X86 inline assembly C++ -*-===//
36 return Reg == X86::RSP || Reg == X86::ESP || Reg == X86::SP;
104 case X86::MOV8mi:
105 case X86::MOV8mr:
106 case X86::MOV8rm:
109 case X86::MOV16mi:
110 case X86::MOV16mr:
111 case X86::MOV16rm:
114 case X86::MOV32mi:
115 case X86::MOV32mr:
116 case X86::MOV32rm:
119 case X86::MOV64mi32:
120 case X86::MOV64mr:
121 case X86::MOV64rm:
124 case X86::MOVAPDmr:
125 case X86::MOVAPSmr:
126 case X86::MOVAPDrm:
127 case X86::MOVAPSrm:
161 EmitInstruction(Out, MCInstBuilder(X86::CLD));
162 EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
164 EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::ESP)
165 .addReg(X86::ESP).addImm(-16));
166 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(AddressReg));
173 EmitInstruction(Out, MCInstBuilder(X86::CALLpcrel32).addExpr(FnExpr));
180 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
181 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX));
182 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EDX));
183 EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
187 Inst.setOpcode(X86::LEA32r);
188 Inst.addOperand(MCOperand::CreateReg(X86::EAX));
194 Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX));
195 EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX)
196 .addReg(X86::ECX).addImm(3));
200 Inst.setOpcode(X86::MOV8rm);
201 Inst.addOperand(MCOperand::CreateReg(X86::CL));
204 X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
210 MCInstBuilder(X86::TEST8rr).addReg(X86::CL).addReg(X86::CL));
213 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
216 Out, MCInstBuilder(X86::MOV32rr).addReg(X86::EDX).addReg(X86::EAX));
217 EmitInstruction(Out, MCInstBuilder(X86::AND32ri).addReg(X86::EDX)
218 .addReg(X86::EDX).addImm(7));
225 Inst.setOpcode(X86::LEA32r);
226 Inst.addOperand(MCOperand::CreateReg(X86::EDX));
230 X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc()));
236 EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8).addReg(X86::EDX)
237 .addReg(X86::EDX).addImm(3));
245 Out, MCInstBuilder(X86::MOVSX32rr8).addReg(X86::ECX).addReg(X86::CL));
247 Out, MCInstBuilder(X86::CMP32rr).addReg(X86::EDX).addReg(X86::ECX));
248 EmitInstruction(Out, MCInstBuilder(X86::JL_4).addExpr(DoneExpr));
250 EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite, X86::EAX);
253 EmitInstruction(Out, MCInstBuilder(X86::POPF32));
254 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EDX));
255 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::ECX));
256 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
262 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
263 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX));
264 EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
268 Inst.setOpcode(X86::LEA32r);
269 Inst.addOperand(MCOperand::CreateReg(X86::EAX));
274 Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX));
275 EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX)
276 .addReg(X86::ECX).addImm(3));
281 Inst.setOpcode(X86::CMP8mi);
284 Inst.setOpcode(X86::CMP16mi);
292 X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
299 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
301 EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite, X86::EAX);
304 EmitInstruction(Out, MCInstBuilder(X86::POPF32));
305 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::ECX));
306 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
327 Inst.setOpcode(X86::LEA64r);
328 Inst.addOperand(MCOperand::CreateReg(X86::RSP));
332 X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc()));
339 EmitInstruction(Out, MCInstBuilder(X86::CLD));
340 EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
342 EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::RSP)
343 .addReg(X86::RSP).addImm(-16));
349 EmitInstruction(Out, MCInstBuilder(X86::CALL64pcrel32).addExpr(FnExpr));
357 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
358 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RCX));
359 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RDI));
360 EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
363 Inst.setOpcode(X86::LEA64r);
364 Inst.addOperand(MCOperand::CreateReg(X86::RDI));
369 Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RAX).addReg(X86::RDI));
370 EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX)
371 .addReg(X86::RAX).addImm(3));
374 Inst.setOpcode(X86::MOV8rm);
375 Inst.addOperand(MCOperand::CreateReg(X86::AL));
378 X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc()));
384 MCInstBuilder(X86::TEST8rr).addReg(X86::AL).addReg(X86::AL));
387 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
390 Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EDI));
391 EmitInstruction(Out, MCInstBuilder(X86::AND32ri).addReg(X86::ECX)
392 .addReg(X86::ECX).addImm(7));
399 Inst.setOpcode(X86::LEA32r);
400 Inst.addOperand(MCOperand::CreateReg(X86::ECX));
404 X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
410 EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8).addReg(X86::ECX)
411 .addReg(X86::ECX).addImm(3));
419 Out, MCInstBuilder(X86::MOVSX32rr8).addReg(X86::EAX).addReg(X86::AL));
421 Out, MCInstBuilder(X86::CMP32rr).addReg(X86::ECX).addReg(X86::EAX));
422 EmitInstruction(Out, MCInstBuilder(X86::JL_4).addExpr(DoneExpr));
427 EmitInstruction(Out, MCInstBuilder(X86::POPF64));
428 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RDI));
429 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RCX));
430 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RAX));
438 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
439 EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
443 Inst.setOpcode(X86::LEA64r);
444 Inst.addOperand(MCOperand::CreateReg(X86::RAX));
448 EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX)
449 .addReg(X86::RAX).addImm(3));
454 Inst.setOpcode(X86::CMP8mi);
457 Inst.setOpcode(X86::CMP16mi);
465 X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc()));
473 EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
478 EmitInstruction(Out, MCInstBuilder(X86::POPF64));
479 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RAX));
499 if ((STI.getFeatureBits() & X86::Mode32Bit) != 0)
501 if ((STI.getFeatureBits() & X86::Mode64Bit) != 0)