Cross Reference: /external/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

Lines Matching refs:X86
1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
712     return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
716     return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
720     return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
724         (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit);
728                     (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit)));
778     if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
779         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
780          X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
781         IndexReg != X86::RIZ) {
785     if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
786         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
787          X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
788         IndexReg != X86::EIZ){
792     if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {
793       if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
794           X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
798       if (((BaseReg == X86::BX || BaseReg == X86::BP) &&
799            IndexReg != X86::SI && IndexReg != X86::DI) ||
800           ((BaseReg == X86::SI || BaseReg == X86::DI) &&
801            IndexReg != X86::BX && IndexReg != X86::BP)) {
821   if (X86MCRegisterClasses[X86::GR16RegClassID].contains(siReg))
822     return X86MCRegisterClasses[X86::GR16RegClassID].contains(diReg);
823   if (X86MCRegisterClasses[X86::GR32RegClassID].contains(siReg))
824     return X86MCRegisterClasses[X86::GR32RegClassID].contains(diReg);
825   if (X86MCRegisterClasses[X86::GR64RegClassID].contains(siReg))
826     return X86MCRegisterClasses[X86::GR64RegClassID].contains(diReg);
863     if (RegNo == X86::RIZ ||
864         X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
874     RegNo = X86::ST0;
887     case 0: RegNo = X86::ST0; break;
888     case 1: RegNo = X86::ST1; break;
889     case 2: RegNo = X86::ST2; break;
890     case 3: RegNo = X86::ST3; break;
891     case 4: RegNo = X86::ST4; break;
892     case 5: RegNo = X86::ST5; break;
893     case 6: RegNo = X86::ST6; break;
894     case 7: RegNo = X86::ST7; break;
913     case '0': RegNo = X86::DR0; break;
914     case '1': RegNo = X86::DR1; break;
915     case '2': RegNo = X86::DR2; break;
916     case '3': RegNo = X86::DR3; break;
917     case '4': RegNo = X86::DR4; break;
918     case '5': RegNo = X86::DR5; break;
919     case '6': RegNo = X86::DR6; break;
920     case '7': RegNo = X86::DR7; break;
942     is64BitMode() ? X86::RSI : (is32BitMode() ? X86::ESI : X86::SI);
950     is64BitMode() ? X86::RDI : (is32BitMode() ? X86::EDI : X86::DI);
988         is64BitMode() ? X86::RBX : (is32BitMode() ? X86::EBX : X86::BX);
1479       is64BitMode() ? X86::RBX : (is32BitMode() ? X86::EBX : X86::BX);
1621     if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
1649   if(STI.getFeatureBits() & X86::FeatureAVX512) {
1777     if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
1818 	  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
1856   if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
1857       (is64BitMode() || (BaseReg != X86::BX && BaseReg != X86::BP &&
1858                          BaseReg != X86::SI && BaseReg != X86::DI)) &&
1859       BaseReg != X86::DX) {
1864       X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
2033       Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
2036       Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
2047       Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
2050       Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
2178   return convertToSExti8(Inst, Opcode, X86::AX, isCmp);
2187   return convertToSExti8(Inst, Opcode, X86::EAX, isCmp);
2196   return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
2202   case X86::AND16i16: return convert16i16to16ri8(Inst, X86::AND16ri8);
2203   case X86::AND32i32: return convert32i32to32ri8(Inst, X86::AND32ri8);
2204   case X86::AND64i32: return convert64i32to64ri8(Inst, X86::AND64ri8);
2205   case X86::XOR16i16: return convert16i16to16ri8(Inst, X86::XOR16ri8);
2206   case X86::XOR32i32: return convert32i32to32ri8(Inst, X86::XOR32ri8);
2207   case X86::XOR64i32: return convert64i32to64ri8(Inst, X86::XOR64ri8);
2208   case X86::OR16i16:  return convert16i16to16ri8(Inst, X86::OR16ri8);
2209   case X86::OR32i32:  return convert32i32to32ri8(Inst, X86::OR32ri8);
2210   case X86::OR64i32:  return convert64i32to64ri8(Inst, X86::OR64ri8);
2211   case X86::CMP16i16: return convert16i16to16ri8(Inst, X86::CMP16ri8, true);
2212   case X86::CMP32i32: return convert32i32to32ri8(Inst, X86::CMP32ri8, true);
2213   case X86::CMP64i32: return convert64i32to64ri8(Inst, X86::CMP64ri8, true);
2214   case X86::ADD16i16: return convert16i16to16ri8(Inst, X86::ADD16ri8);
2215   case X86::ADD32i32: return convert32i32to32ri8(Inst, X86::ADD32ri8);
2216   case X86::ADD64i32: return convert64i32to64ri8(Inst, X86::ADD64ri8);
2217   case X86::SUB16i16: return convert16i16to16ri8(Inst, X86::SUB16ri8);
2218   case X86::SUB32i32: return convert32i32to32ri8(Inst, X86::SUB32ri8);
2219   case X86::SUB64i32: return convert64i32to64ri8(Inst, X86::SUB64ri8);
2220   case X86::ADC16i16: return convert16i16to16ri8(Inst, X86::ADC16ri8);
2221   case X86::ADC32i32: return convert32i32to32ri8(Inst, X86::ADC32ri8);
2222   case X86::ADC64i32: return convert64i32to64ri8(Inst, X86::ADC64ri8);
2223   case X86::SBB16i16: return convert16i16to16ri8(Inst, X86::SBB16ri8);
2224   case X86::SBB32i32: return convert32i32to32ri8(Inst, X86::SBB32ri8);
2225   case X86::SBB64i32: return convert64i32to64ri8(Inst, X86::SBB64ri8);
2226   case X86::VMOVAPDrr:
2227   case X86::VMOVAPDYrr:
2228   case X86::VMOVAPSrr:
2229   case X86::VMOVAPSYrr:
2230   case X86::VMOVDQArr:
2231   case X86::VMOVDQAYrr:
2232   case X86::VMOVDQUrr:
2233   case X86::VMOVDQUYrr:
2234   case X86::VMOVUPDrr:
2235   case X86::VMOVUPDYrr:
2236   case X86::VMOVUPSrr:
2237   case X86::VMOVUPSYrr: {
2245     case X86::VMOVAPDrr:  NewOpc = X86::VMOVAPDrr_REV;  break;
2246     case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
2247     case X86::VMOVAPSrr:  NewOpc = X86::VMOVAPSrr_REV;  break;
2248     case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
2249     case X86::VMOVDQArr:  NewOpc = X86::VMOVDQArr_REV;  break;
2250     case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
2251     case X86::VMOVDQUrr:  NewOpc = X86::VMOVDQUrr_REV;  break;
2252     case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
2253     case X86::VMOVUPDrr:  NewOpc = X86::VMOVUPDrr_REV;  break;
2254     case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
2255     case X86::VMOVUPSrr:  NewOpc = X86::VMOVUPSrr_REV;  break;
2256     case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
2261   case X86::VMOVSDrr:
2262   case X86::VMOVSSrr: {
2269     case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV;   break;
2270     case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV;   break;
2305     Inst.setOpcode(X86::WAIT);
2578       SwitchMode(X86::Mode16Bit);
2584       SwitchMode(X86::Mode32Bit);
2590       SwitchMode(X86::Mode64Bit);