Lines Matching refs:Desc

68                           const MCInstrDesc *Desc) const;
72 const MCInstrDesc *Desc) const;
78 void emitInstruction(MachineInstr &MI, const MCInstrDesc *Desc);
147 const MCInstrDesc &Desc = I->getDesc();
148 emitInstruction(*I, &Desc);
150 if (Desc.getOpcode() == X86::MOVPC32r)
165 const MCInstrDesc &Desc = MI.getDesc();
168 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
170 if (Desc.TSFlags & X86II::REX_W)
173 unsigned NumOps = Desc.getNumOperands();
176 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
189 switch (Desc.TSFlags & X86II::FormMask) {
605 const MCInstrDesc *Desc = &II->get(Opcode);
606 MI.setDesc(*Desc);
607 return Desc;
658 const MCInstrDesc *Desc) const {
663 switch (Desc->TSFlags & X86II::OpPrefixMask) {
682 switch (Desc->TSFlags & X86II::OpMapMask) {
690 switch (Desc->TSFlags & X86II::OpMapMask) {
748 const MCInstrDesc *Desc) const {
838 unsigned NumOps = Desc->getNumOperands();
840 if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) == 0)
842 else if (NumOps > 3 && Desc->getOperandConstraint(2, MCOI::TIED_TO) == 0) {
843 assert(Desc->getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1);
1006 const MCInstrDesc *Desc) {
1010 switch (Desc->getOpcode()) {
1011 case X86::ADD16rr_DB: Desc = UpdateOp(MI, II, X86::OR16rr); break;
1012 case X86::ADD32rr_DB: Desc = UpdateOp(MI, II, X86::OR32rr); break;
1013 case X86::ADD64rr_DB: Desc = UpdateOp(MI, II, X86::OR64rr); break;
1014 case X86::ADD16ri_DB: Desc = UpdateOp(MI, II, X86::OR16ri); break;
1015 case X86::ADD32ri_DB: Desc = UpdateOp(MI, II, X86::OR32ri); break;
1016 case X86::ADD64ri32_DB: Desc = UpdateOp(MI, II, X86::OR64ri32); break;
1017 case X86::ADD16ri8_DB: Desc = UpdateOp(MI, II, X86::OR16ri8); break;
1018 case X86::ADD32ri8_DB: Desc = UpdateOp(MI, II, X86::OR32ri8); break;
1019 case X86::ADD64ri8_DB: Desc = UpdateOp(MI, II, X86::OR64ri8); break;
1020 case X86::ACQUIRE_MOV8rm: Desc = UpdateOp(MI, II, X86::MOV8rm); break;
1021 case X86::ACQUIRE_MOV16rm: Desc = UpdateOp(MI, II, X86::MOV16rm); break;
1022 case X86::ACQUIRE_MOV32rm: Desc = UpdateOp(MI, II, X86::MOV32rm); break;
1023 case X86::ACQUIRE_MOV64rm: Desc = UpdateOp(MI, II, X86::MOV64rm); break;
1024 case X86::RELEASE_MOV8mr: Desc = UpdateOp(MI, II, X86::MOV8mr); break;
1025 case X86::RELEASE_MOV16mr: Desc = UpdateOp(MI, II, X86::MOV16mr); break;
1026 case X86::RELEASE_MOV32mr: Desc = UpdateOp(MI, II, X86::MOV32mr); break;
1027 case X86::RELEASE_MOV64mr: Desc = UpdateOp(MI, II, X86::MOV64mr); break;
1033 unsigned Opcode = Desc->Opcode;
1036 unsigned NumOps = Desc->getNumOperands();
1038 if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) == 0)
1040 else if (NumOps > 3 && Desc->getOperandConstraint(2, MCOI::TIED_TO) == 0) {
1041 assert(Desc->getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1);
1047 uint64_t TSFlags = Desc->TSFlags;
1064 if (Desc->TSFlags & X86II::LOCK)
1071 if (Desc->TSFlags & X86II::REP)
1092 emitOpcodePrefix(TSFlags, MemoryOperand, MI, Desc);
1094 emitVEXOpcodePrefix(TSFlags, MemoryOperand, MI, Desc);
1096 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(Desc->TSFlags);
1147 emitConstant(0, X86II::getSizeOfImm(Desc->TSFlags));
1198 emitConstant(Imm, X86II::getSizeOfImm(Desc->TSFlags));
1200 emitConstant(MO.getImm(), X86II::getSizeOfImm(Desc->TSFlags));
1212 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
1293 X86II::getSizeOfImm(Desc->TSFlags) : 0;
1310 uint64_t Form = (Desc->TSFlags & X86II::FormMask);
1318 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
1350 X86II::getSizeOfImm(Desc->TSFlags) : 4) : 0;
1353 uint64_t Form = (Desc->TSFlags & X86II::FormMask);
1362 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
1486 X86II::getSizeOfImm(Desc->TSFlags));