Lines Matching refs:LHS
3537 /// specific condition code, returning the condition code and the LHS/RHS of the
3540 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3576 // If LHS is a foldable load, but RHS is not, flip the condition.
3577 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3580 std::swap(LHS, RHS);
3589 std::swap(LHS, RHS);
9638 SDValue LHS = Op.getOperand(1);
9668 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
9672 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11564 e += 2; // 2 more nodes (LHS and RHS) are pushed.
11616 SDValue LHS = VecIns[Slot];
11618 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
11957 SDValue LHS, RHS;
11973 LHS = Op1;
11982 LHS = AndLHS.getOperand(0);
11988 LHS = AndLHS;
11989 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
11993 if (LHS.getNode()) {
11994 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
11999 if (LHS.getValueType() == MVT::i8 ||
12000 LHS.getValueType() == MVT::i16)
12001 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12005 if (LHS.getValueType() != RHS.getValueType())
12006 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12008 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12074 // Extract the LHS vectors
12075 SDValue LHS = Op.getOperand(0);
12076 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12077 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12631 SDValue LHS = Cond.getOperand(0);
12646 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
12649 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
12651 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
12909 SDValue LHS = Cond.getOperand(0);
12941 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
12944 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
12946 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
13574 SDValue LHS = Op.getOperand(1);
13576 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
13578 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
13912 SDValue LHS = Op.getOperand(1);
13915 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
13923 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
13926 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
14994 // Extract the LHS vectors
14995 SDValue LHS = Op.getOperand(0);
14996 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14997 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15774 SDValue LHS = N->getOperand(0);
15820 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
15833 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
15865 // Extract the LHS vectors
15866 SDValue LHS = Op.getOperand(0);
15867 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15868 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
19091 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
19124 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19142 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
19169 SDValue LHS = N->getOperand(1);
19206 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
19216 // Get the LHS/RHS of the select.
19217 SDValue LHS = N->getOperand(1);
19219 EVT VT = LHS.getValueType();
19234 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19242 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
19244 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
19246 std::swap(LHS, RHS);
19254 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
19261 std::swap(LHS, RHS);
19272 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
19280 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
19282 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
19284 std::swap(LHS, RHS);
19291 std::swap(LHS, RHS);
19299 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
19308 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
19309 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19311 std::swap(LHS, RHS);
19318 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
19325 std::swap(LHS, RHS);
19334 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19343 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
19344 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19346 std::swap(LHS, RHS);
19353 std::swap(LHS, RHS);
19363 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
19373 EVT OpVT = LHS.getValueType();
19379 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
19384 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
19387 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
19409 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
19412 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
19491 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19501 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
19520 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
19524 Other = LHS;
19572 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
19578 // Extract the LHS vectors
19579 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
19580 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
19587 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
19591 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
19593 return DAG.getNode(Opc, DL, VT, LHS, RHS);
19606 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
19612 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
19621 std::swap(LHS, RHS);
19637 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
19650 SDValue A = LHS;
19703 std::swap(LHS, RHS);
19708 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
19762 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
19908 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
20598 // Check LHS for vnot
21250 /// and return the operands for the horizontal operation in LHS and RHS. A
21259 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
21260 /// A horizontal-op B, for some already available A and B, and if so then LHS is
21264 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
21269 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
21271 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
21275 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
21279 MVT VT = LHS.getSimpleValueType();
21293 // View LHS in the form
21294 // LHS = VECTOR_SHUFFLE A, B, LMask
21295 // If LHS is not a shuffle then pretend it is the shuffle
21296 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
21301 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21302 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
21303 A = LHS.getOperand(0);
21304 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
21305 B = LHS.getOperand(1);
21306 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
21309 if (LHS.getOpcode() != ISD::UNDEF)
21310 A = LHS;
21346 // At this point LHS and RHS are equivalent to
21347 // LHS = VECTOR_SHUFFLE A, B, LMask
21370 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
21379 SDValue LHS = N->getOperand(0);
21385 isHorizontalBinOp(LHS, RHS, true))
21386 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
21394 SDValue LHS = N->getOperand(0);
21400 isHorizontalBinOp(LHS, RHS, false))
21401 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
21645 SDValue LHS = N->getOperand(0);
21650 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
21651 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
21652 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
21654 LHS.getValueType(), RHS, LHS.getOperand(1));
21662 RHS.getValueType(), LHS, RHS.getOperand(1));
21668 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
21669 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
21670 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
21681 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
21683 return DAG.getNOT(DL, LHS.getOperand(0), VT);
21684 return LHS.getOperand(0);
21837 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
21840 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
21923 // X86 can't encode an immediate LHS of a sub. See if we can push the
21927 // immediate. Then add one to the LHS of the sub so we can turn