Cross Reference: /external/llvm/lib/Target/XCore/XCoreFrameLowering.cpp

Lines Matching defs:MBB
61 static void EmitDefCfaRegister(MachineBasicBlock &MBB,
67   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
71 static void EmitDefCfaOffset(MachineBasicBlock &MBB,
77   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
81 static void EmitCfiOffset(MachineBasicBlock &MBB,
87   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
97 static void IfNeededExtSP(MachineBasicBlock &MBB,
107     BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
110       EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
121 static void IfNeededLDAWSP(MachineBasicBlock &MBB,
129     BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm);
176 getFrameIndexMMO(MachineBasicBlock &MBB, int FrameIndex, unsigned flags) {
177   MachineFunction *MF = MBB.getParent();
191 RestoreSpillList(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
198     IfNeededLDAWSP(MBB, MBBI, dl, TII, OffsetFromTop, RemainingAdj);
201     BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg)
203       .addMemOperand(getFrameIndexMMO(MBB, SpillList[i].FI,
223   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
224   MachineBasicBlock::iterator MBBI = MBB.begin();
241     BuildMI(MBB, MBBI, dl, TII.get(XCore::LDWSP_ru6), XCore::R11).addImm(0);
262     MBB.addLiveIn(XCore::LR);
263     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
267       EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
269       EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, 0);
282     IfNeededExtSP(MBB, MBBI, dl, TII, MMI, OffsetFromTop, Adjusted, FrameSize,
286     MBB.addLiveIn(SpillList[i].Reg);
287     BuildMI(MBB, MBBI, dl, TII.get(Opcode))
290       .addMemOperand(getFrameIndexMMO(MBB, SpillList[i].FI,
294       EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, SpillList[i].Offset);
299   IfNeededExtSP(MBB, MBBI, dl, TII, MMI, FrameSize, Adjusted, FrameSize,
305     BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0);
307       EmitDefCfaRegister(MBB, MBBI, dl, TII, MMI,
320       EmitCfiOffset(MBB, Pos, dl, TII, MMI, DRegNum, Offset);
328       EmitCfiOffset(MBB, MBBI, dl, TII, MMI,
331       EmitCfiOffset(MBB, MBBI, dl, TII, MMI,
339                                      MachineBasicBlock &MBB) const {
341   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
359     RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
364     BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(EhStackReg);
365     BuildMI(MBB, MBBI, dl, TII.get(XCore::BAU_1r)).addReg(EhHandlerReg);
366     MBB.erase(MBBI);  // Erase the previous return instruction.
378     BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(FramePtr);
383   RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
387     IfNeededLDAWSP(MBB, MBBI, dl, TII, 0, RemainingAdj);
393       MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode))
397       MBB.erase(MBBI);  // Erase the previous return instruction.
401       BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(RemainingAdj);
408 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
415   MachineFunction *MF = MBB.getParent();
421   if (MI != MBB.end() && !MI->isDebugValue())
431     MBB.addLiveIn(Reg);
433     TII.storeRegToStackSlot(MBB, MI, Reg, true, it->getFrameIdx(), RC, TRI);
444 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
448   MachineFunction *MF = MBB.getParent();
450   bool AtStart = MI == MBB.begin();
461     TII.loadRegFromStackSlot(MBB, MI, Reg, it->getFrameIdx(), RC, TRI);
462     assert(MI != MBB.begin() &&
467       MI = MBB.begin();
479 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
521       MBB.insert(I, New);
525   MBB.erase(I);