Cross Reference: /external/llvm/llvm-tblgen-rules.mk

Lines Matching refs:td
2 ## Commands for running tblgen to compile a td file
4 define transform-td-to-out
6 	$(call transform-host-td-to-out,$(1)),	\
7 	$(call transform-device-td-to-out,$(1)))
11 ## TableGen: Compile .td files to .inc.
32 tblgen_td_deps := $(tblgen_source_dir)/../*.td
34 tblgen_td_deps := $(tblgen_source_dir)/*.td
39 # The directory and the .td directory is not the same.
43 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
45 	$(call transform-td-to-out, register-info)
48 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
50 	$(call transform-td-to-out,instr-info)
53 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
55 	$(call transform-td-to-out,subtarget)
60 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
62 	$(call transform-td-to-out, register-info)
65 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
67 	$(call transform-td-to-out,instr-info)
70 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
72 	$(call transform-td-to-out,subtarget)
77 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
79 	$(call transform-td-to-out, register-info)
82 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
84 	$(call transform-td-to-out,instr-info)
87 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
89 	$(call transform-td-to-out,subtarget)
95 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td \
97 	$(call transform-td-to-out,register-info)
102 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td \
104 	$(call transform-td-to-out,instr-info)
109 $(generated_sources)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td \
111 	$(call transform-td-to-out,asm-writer)
116 $(generated_sources)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td \
118 	$(call transform-td-to-out,asm-writer -asmwriternum=1)
123 $(generated_sources)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td \
125 	$(call transform-td-to-out,asm-matcher)
130 $(generated_sources)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td \
132 	$(call transform-td-to-out,emitter)
137 $(generated_sources)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td \
139 	$(call transform-td-to-out,emitter -mc-emitter)
144 $(generated_sources)/%GenMCPseudoLowering.inc: $(tblgen_source_dir)/%.td \
146 	$(call transform-td-to-out,pseudo-lowering)
151 $(generated_sources)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td \
153 	$(call transform-td-to-out,dag-isel)
158 $(generated_sources)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td \
160 	$(call transform-td-to-out,disassembler)
165 $(generated_sources)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td \
167 	$(call transform-td-to-out,enhanced-disassembly-info)
172 $(generated_sources)/%GenFastISel.inc: $(tblgen_source_dir)/%.td \
174 	$(call transform-td-to-out,fast-isel)
179 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td \
181 	$(call transform-td-to-out,subtarget)
186 $(generated_sources)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td \
188 	$(call transform-td-to-out,callingconv)
193 $(generated_sources)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td \
195 	$(call transform-td-to-out,tgt_intrinsics)
200 $(generated_sources)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td \
202 	$(call transform-td-to-out,arm-decoder)