Cross Reference: /external/llvm/test/MC/AArch64/arm64-logical-encoding.s

Lines Matching refs:w1
10   and   w1, w2, #15
15   ands  w1, w2, #15
20 ; CHECK: and  w1, w2, #0xf           ; encoding: [0x41,0x0c,0x00,0x12]
25 ; CHECK: ands w1, w2, #0xf           ; encoding: [0x41,0x0c,0x00,0x72]
28   eor w1, w2, #0x4000
31 ; CHECK: eor w1, w2, #0x4000         ; encoding: [0x41,0x00,0x12,0x52]
34   orr w1, w2, #0x4000
37 ; CHECK: orr w1, w2, #0x4000         ; encoding: [0x41,0x00,0x12,0x32]
50   and   w1, w2, w3
52   and   w1, w2, w3, lsl #2
54   and   w1, w2, w3, lsr #2
56   and   w1, w2, w3, asr #2
58   and   w1, w2, w3, ror #2
61 ; CHECK: and  w1, w2, w3             ; encoding: [0x41,0x00,0x03,0x0a]
63 ; CHECK: and  w1, w2, w3, lsl #2     ; encoding: [0x41,0x08,0x03,0x0a]
65 ; CHECK: and  w1, w2, w3, lsr #2     ; encoding: [0x41,0x08,0x43,0x0a]
67 ; CHECK: and  w1, w2, w3, asr #2     ; encoding: [0x41,0x08,0x83,0x0a]
69 ; CHECK: and  w1, w2, w3, ror #2     ; encoding: [0x41,0x08,0xc3,0x0a]
72   ands  w1, w2, w3
74   ands  w1, w2, w3, lsl #2
76   ands  w1, w2, w3, lsr #2
78   ands  w1, w2, w3, asr #2
80   ands  w1, w2, w3, ror #2
83 ; CHECK: ands w1, w2, w3             ; encoding: [0x41,0x00,0x03,0x6a]
85 ; CHECK: ands w1, w2, w3, lsl #2     ; encoding: [0x41,0x08,0x03,0x6a]
87 ; CHECK: ands w1, w2, w3, lsr #2     ; encoding: [0x41,0x08,0x43,0x6a]
89 ; CHECK: ands w1, w2, w3, asr #2     ; encoding: [0x41,0x08,0x83,0x6a]
91 ; CHECK: ands w1, w2, w3, ror #2     ; encoding: [0x41,0x08,0xc3,0x6a]
94   bic w1, w2, w3
96   bic w1, w2, w3, lsl #3
98   bic w1, w2, w3, lsr #3
100   bic w1, w2, w3, asr #3
102   bic w1, w2, w3, ror #3
105 ; CHECK: bic w1, w2, w3              ; encoding: [0x41,0x00,0x23,0x0a]
107 ; CHECK: bic w1, w2, w3, lsl #3      ; encoding: [0x41,0x0c,0x23,0x0a]
109 ; CHECK: bic w1, w2, w3, lsr #3      ; encoding: [0x41,0x0c,0x63,0x0a]
111 ; CHECK: bic w1, w2, w3, asr #3      ; encoding: [0x41,0x0c,0xa3,0x0a]
113 ; CHECK: bic w1, w2, w3, ror #3      ; encoding: [0x41,0x0c,0xe3,0x0a]
116   bics w1, w2, w3
118   bics w1, w2, w3, lsl #3
120   bics w1, w2, w3, lsr #3
122   bics w1, w2, w3, asr #3
124   bics w1, w2, w3, ror #3
127 ; CHECK: bics w1, w2, w3             ; encoding: [0x41,0x00,0x23,0x6a]
129 ; CHECK: bics w1, w2, w3, lsl #3     ; encoding: [0x41,0x0c,0x23,0x6a]
131 ; CHECK: bics w1, w2, w3, lsr #3     ; encoding: [0x41,0x0c,0x63,0x6a]
133 ; CHECK: bics w1, w2, w3, asr #3     ; encoding: [0x41,0x0c,0xa3,0x6a]
135 ; CHECK: bics w1, w2, w3, ror #3     ; encoding: [0x41,0x0c,0xe3,0x6a]
138   eon w1, w2, w3
140   eon w1, w2, w3, lsl #4
142   eon w1, w2, w3, lsr #4
144   eon w1, w2, w3, asr #4
146   eon w1, w2, w3, ror #4
149 ; CHECK: eon w1, w2, w3              ; encoding: [0x41,0x00,0x23,0x4a]
151 ; CHECK: eon w1, w2, w3, lsl #4      ; encoding: [0x41,0x10,0x23,0x4a]
153 ; CHECK: eon w1, w2, w3, lsr #4      ; encoding: [0x41,0x10,0x63,0x4a]
155 ; CHECK: eon w1, w2, w3, asr #4      ; encoding: [0x41,0x10,0xa3,0x4a]
157 ; CHECK: eon w1, w2, w3, ror #4      ; encoding: [0x41,0x10,0xe3,0x4a]
160   eor w1, w2, w3
162   eor w1, w2, w3, lsl #5
164   eor w1, w2, w3, lsr #5
166   eor w1, w2, w3, asr #5
168   eor w1, w2, w3, ror #5
171 ; CHECK: eor w1, w2, w3              ; encoding: [0x41,0x00,0x03,0x4a]
173 ; CHECK: eor w1, w2, w3, lsl #5      ; encoding: [0x41,0x14,0x03,0x4a]
175 ; CHECK: eor w1, w2, w3, lsr #5      ; encoding: [0x41,0x14,0x43,0x4a]
177 ; CHECK: eor w1, w2, w3, asr #5      ; encoding: [0x41,0x14,0x83,0x4a]
179 ; CHECK: eor w1, w2, w3, ror #5      ; encoding: [0x41,0x14,0xc3,0x4a]
182   orr w1, w2, w3
184   orr w1, w2, w3, lsl #6
186   orr w1, w2, w3, lsr #6
188   orr w1, w2, w3, asr #6
190   orr w1, w2, w3, ror #6
193 ; CHECK: orr w1, w2, w3              ; encoding: [0x41,0x00,0x03,0x2a]
195 ; CHECK: orr w1, w2, w3, lsl #6      ; encoding: [0x41,0x18,0x03,0x2a]
197 ; CHECK: orr w1, w2, w3, lsr #6      ; encoding: [0x41,0x18,0x43,0x2a]
199 ; CHECK: orr w1, w2, w3, asr #6      ; encoding: [0x41,0x18,0x83,0x2a]
201 ; CHECK: orr w1, w2, w3, ror #6      ; encoding: [0x41,0x18,0xc3,0x2a]
204   orn w1, w2, w3
206   orn w1, w2, w3, lsl #7
208   orn w1, w2, w3, lsr #7
210   orn w1, w2, w3, asr #7
212   orn w1, w2, w3, ror #7
215 ; CHECK: orn w1, w2, w3              ; encoding: [0x41,0x00,0x23,0x2a]
217 ; CHECK: orn w1, w2, w3, lsl #7      ; encoding: [0x41,0x1c,0x23,0x2a]
219 ; CHECK: orn w1, w2, w3, lsr #7      ; encoding: [0x41,0x1c,0x63,0x2a]
221 ; CHECK: orn w1, w2, w3, asr #7      ; encoding: [0x41,0x1c,0xa3,0x2a]
223 ; CHECK: orn w1, w2, w3, ror #7      ; encoding: [0x41,0x1c,0xe3,0x2a]