Lines Matching defs:caps
34 void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps)
39 caps->family = CHIP_FAMILY_##chipfamily; \
51 caps->high_second_pipe = FALSE;
52 caps->num_vert_fpus = 0;
53 caps->hiz_ram = 0;
54 caps->zmask_ram = 0;
57 switch (caps->family) {
60 caps->high_second_pipe = TRUE;
61 caps->num_vert_fpus = 4;
62 caps->hiz_ram = R300_HIZ_LIMIT;
63 caps->zmask_ram = PIPE_ZMASK_SIZE;
68 caps->high_second_pipe = TRUE;
69 caps->num_vert_fpus = 2;
70 caps->zmask_ram = RV3xx_ZMASK_SIZE;
74 caps->high_second_pipe = TRUE;
75 caps->num_vert_fpus = 2;
76 caps->hiz_ram = R300_HIZ_LIMIT;
77 caps->zmask_ram = RV3xx_ZMASK_SIZE;
88 caps->zmask_ram = RV3xx_ZMASK_SIZE;
97 caps->num_vert_fpus = 6;
98 caps->hiz_ram = R300_HIZ_LIMIT;
99 caps->zmask_ram = PIPE_ZMASK_SIZE;
103 caps->num_vert_fpus = 8;
104 caps->hiz_ram = R300_HIZ_LIMIT;
105 caps->zmask_ram = PIPE_ZMASK_SIZE;
109 caps->num_vert_fpus = 2;
110 caps->hiz_ram = R300_HIZ_LIMIT;
111 caps->zmask_ram = PIPE_ZMASK_SIZE;
115 caps->num_vert_fpus = 5;
116 caps->hiz_ram = RV530_HIZ_LIMIT;
117 caps->zmask_ram = PIPE_ZMASK_SIZE;
123 caps->num_vert_fpus = 8;
124 caps->hiz_ram = RV530_HIZ_LIMIT;
125 caps->zmask_ram = PIPE_ZMASK_SIZE;
129 caps->num_tex_units = 16;
130 caps->is_r400 = caps->family >= CHIP_FAMILY_R420 && caps->family < CHIP_FAMILY_RV515;
131 caps->is_r500 = caps->family >= CHIP_FAMILY_RV515;
132 caps->is_rv350 = caps->family >= CHIP_FAMILY_RV350;
133 caps->z_compress = caps->is_rv350 ? R300_ZCOMP_8X8 : R300_ZCOMP_4X4;
134 caps->dxtc_swizzle = caps->is_r400 || caps->is_r500;
135 caps->has_us_format = caps->family == CHIP_FAMILY_R520;
136 caps->has_tcl = caps->num_vert_fpus > 0;
138 if (caps->has_tcl) {
139 caps->has_tcl = debug_get_bool_option("RADEON_NO_TCL", FALSE) ? FALSE : TRUE;