Lines Matching refs:res
58 struct evergreen_compute_resource* res,
61 res->cs[res->cs_end++] = value;
70 struct evergreen_compute_resource* res,
77 evergreen_emit_raw_reg_set(res, index, size / 4);
80 res->cs[res->cs_end++] = array[i / 4];
85 struct evergreen_compute_resource* res,
89 evergreen_emit_raw_reg_set(res, index, 1);
90 res->cs[res->cs_end++] = value;
113 struct evergreen_compute_resource* res = &pipe->resources[index];
115 res->enabled = true;
116 res->bo = NULL;
117 res->cs_end = 0;
118 bzero(&res->do_reloc, sizeof(res->do_reloc));
120 return res;
124 struct evergreen_compute_resource* res,
128 res->enabled = 1;
129 int cs_end = res->cs_end;
133 res->cs[cs_end] = PKT3C(PKT3_SET_CONFIG_REG, num, 0);
134 res->cs[cs_end+1] = (index - EVERGREEN_CONFIG_REG_OFFSET) >> 2;
137 res->cs[cs_end] = PKT3C(PKT3_SET_CONTEXT_REG, num, 0);
138 res->cs[cs_end+1] = (index - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
141 res->cs[cs_end] = PKT3C(PKT3_SET_RESOURCE, num, 0);
142 res->cs[cs_end+1] = (index - EVERGREEN_RESOURCE_OFFSET) >> 2;
145 res->cs[cs_end] = PKT3C(PKT3_SET_SAMPLER, num, 0);
146 res->cs[cs_end+1] = (index - EVERGREEN_SAMPLER_OFFSET) >> 2;
149 res->cs[cs_end] = PKT3C(PKT3_SET_CTL_CONST, num, 0);
150 res->cs[cs_end+1] = (index - EVERGREEN_CTL_CONST_OFFSET) >> 2;
153 res->cs[cs_end] = PKT3C(PKT3_SET_LOOP_CONST, num, 0);
154 res->cs[cs_end+1] = (index - EVERGREEN_LOOP_CONST_OFFSET) >> 2;
157 res->cs[cs_end] = PKT3C(PKT3_SET_BOOL_CONST, num, 0);
158 res->cs[cs_end+1] = (index - EVERGREEN_BOOL_CONST_OFFSET) >> 2;
160 res->cs[cs_end] = PKT0(index, num-1);
161 res->cs_end--;
164 res->cs_end += 2;
167 void evergreen_emit_force_reloc(struct evergreen_compute_resource* res)
169 res->do_reloc[res->cs_end] += 1;
270 struct r600_resource *res;
298 res = (struct r600_resource*)surf->base.texture;
304 surf->cb_color_base, res, RADEON_USAGE_READWRITE);
308 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
316 surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
329 struct evergreen_compute_resource* res =
332 evergreen_reg_set(res, R_028728_GDS_ORDERED_WAVE_PER_SE, 1);
333 evergreen_reg_set(res, R_028720_GDS_ADDR_BASE, addr);
334 evergreen_reg_set(res, R_028724_GDS_ADDR_SIZE, size);
345 struct evergreen_compute_resource* res =
348 evergreen_reg_set(res, SX_MEMORY_EXPORT_SIZE, size);
351 evergreen_reg_set(res, SX_MEMORY_EXPORT_BASE, offset);
352 res->bo = bo;
353 res->usage = RADEON_USAGE_WRITE;
354 res->coher_bo_size = size;
355 res->flags = 0;
363 struct evergreen_compute_resource* res =
373 evergreen_reg_set(res, R_03A200_SQ_LOOP_CONST_0 + (160 * 4) + (id * 4),
390 struct evergreen_compute_resource* res =
393 evergreen_reg_set(res,
397 evergreen_reg_set(res, SQ_LSTMP_RING_SIZE, size);
402 evergreen_reg_set(res, SQ_LSTMP_RING_BASE, offset);
403 res->bo = bo;
404 res->usage = RADEON_USAGE_WRITE;
405 res->coher_bo_size = 0;
406 res->flags = 0;
410 evergreen_emit_force_reloc(res);
413 evergreen_reg_set(res,
498 struct evergreen_compute_resource* res =
533 evergreen_emit_raw_value(res, PKT3C(PKT3_SET_RESOURCE, 8, 0));
534 evergreen_emit_raw_value(res, (id+816)*32 >> 2); ///TODO: check this line
535 evergreen_emit_raw_value(res,
540 evergreen_emit_raw_value(res, (S_030004_TEX_HEIGHT(height - 1) |
543 evergreen_emit_raw_value(res, tmp->surface.level[0].offset >> 8);
544 evergreen_emit_raw_value(res, tmp->surface.level[0].offset >> 8);
545 evergreen_emit_raw_value(res, (word4 |
549 evergreen_emit_raw_value(res, (S_030014_LAST_LEVEL(0) |
552 evergreen_emit_raw_value(res, (S_030018_MAX_ANISO(4 /* max 16 samples */)));
553 evergreen_emit_raw_value(res,
557 res->bo = (struct r600_resource*)view->base.texture;
559 res->usage = RADEON_USAGE_READ;
561 res->coher_bo_size = tmp->surface.level[0].offset +
567 evergreen_emit_force_reloc(res);
568 evergreen_emit_force_reloc(res);
576 struct evergreen_compute_resource* res =
581 evergreen_emit_raw_value(res, PKT3C(PKT3_SET_SAMPLER, 3, 0));
582 evergreen_emit_raw_value(res, (id + 90)*3);
583 evergreen_emit_raw_value(res,
591 evergreen_emit_raw_value(res,
595 evergreen_emit_raw_value(res,
611 struct evergreen_compute_resource* res =
618 evergreen_reg_set(res, SQ_ALU_CONST_BUFFER_SIZE_LS_0 + cache_id*4, size);
619 evergreen_reg_set(res, SQ_ALU_CONST_CACHE_LS_0 + cache_id*4, offset >> 8);
620 res->bo = cbo;
621 res->usage = RADEON_USAGE_READ;
622 res->coher_bo_size = size;