Lines Matching defs:rctx
644 void r600_polygon_offset_update(struct r600_context *rctx)
650 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
651 float offset_units = rctx->rasterizer->offset_units;
654 switch (rctx->framebuffer.zsbuf->format) {
677 fui(rctx->rasterizer->offset_scale));
683 fui(rctx->rasterizer->offset_scale));
690 r600_context_pipe_state_set(rctx, &state);
698 struct r600_context *rctx = (struct r600_context *)ctx;
711 if (rctx->family > CHIP_R600)
773 if (rctx->family > CHIP_R600)
800 struct r600_context *rctx = (struct r600_context *)ctx;
856 struct r600_context *rctx = (struct r600_context *)ctx;
927 if (rctx->chip_class >= R700) {
1133 struct r600_context *rctx = (struct r600_context *)ctx;
1140 rctx->clip = *state;
1157 free(rctx->states[R600_PIPE_STATE_CLIP]);
1158 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1159 r600_context_pipe_state_set(rctx, rstate);
1174 void r600_set_scissor_state(struct r600_context *rctx,
1191 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1192 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1193 r600_context_pipe_state_set(rctx, rstate);
1199 struct r600_context *rctx = (struct r600_context *)ctx;
1201 if (rctx->chip_class == R600) {
1202 rctx->scissor_state = *state;
1204 if (!rctx->scissor_enable)
1208 r600_set_scissor_state(rctx, state);
1214 struct r600_context *rctx = (struct r600_context *)ctx;
1220 rctx->viewport = *state;
1229 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1230 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1231 r600_context_pipe_state_set(rctx, rstate);
1254 static void r600_init_color_surface(struct r600_context *rctx,
1258 struct r600_screen *rscreen = rctx->screen;
1270 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1358 if (rctx->chip_class == R600) {
1428 if (!rctx->dummy_cmask ||
1429 rctx->dummy_cmask->buf->size < cmask.size ||
1430 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1434 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1435 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1438 ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1440 pipe_buffer_unmap(&rctx->context, transfer);
1443 &rctx->dummy_cmask->b.b);
1446 if (!rctx->dummy_fmask ||
1447 rctx->dummy_fmask->buf->size < fmask.size ||
1448 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1449 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1450 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1454 &rctx->dummy_fmask->b.b);
1476 static void r600_init_depth_surface(struct r600_context *rctx,
1537 struct r600_context *rctx = (struct r600_context *)ctx;
1539 if (rctx->family == CHIP_R600) {
1583 struct r600_context *rctx = (struct r600_context *)ctx;
1593 bool cb1_force_cmask_fmask = rctx->chip_class == R600 && is_resolve;
1598 r600_flush_framebuffer(rctx, false);
1603 util_copy_framebuffer_state(&rctx->framebuffer, state);
1606 rctx->export_16bpc = true;
1607 rctx->nr_cbufs = state->nr_cbufs;
1608 rctx->cb0_is_integer = state->nr_cbufs &&
1610 rctx->compressed_cb_mask = 0;
1621 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1629 rctx->export_16bpc = false;
1650 rctx->compressed_cb_mask |= 1 << i;
1667 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1668 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1669 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1681 r600_init_depth_surface(rctx, surf);
1737 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1738 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1739 r600_context_pipe_state_set(rctx, rstate);
1742 r600_polygon_offset_update(rctx);
1745 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1746 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1747 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1750 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1751 rctx->alphatest_state.bypass = false;
1752 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1756 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1758 struct radeon_winsys_cs *cs = rctx->cs;
1763 if (rctx->chip_class == R600) {
1786 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1788 struct radeon_winsys_cs *cs = rctx->cs;
1797 if (rctx->chip_class >= R700) {
1816 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1818 struct radeon_winsys_cs *cs = rctx->cs;
1819 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1827 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1847 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1851 static void r600_emit_constant_buffers(struct r600_context *rctx,
1857 struct radeon_winsys_cs *cs = rctx->cs;
1877 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1892 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1899 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1901 r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160,
1906 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1908 r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1913 static void r600_emit_sampler_views(struct r600_context *rctx,
1917 struct radeon_winsys_cs *cs = rctx->cs;
1933 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1943 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1945 r600_emit_sampler_views(rctx, &rctx->vs_samplers.views, 160 + R600_MAX_CONST_BUFFERS);
1948 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1950 r600_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
1953 static void r600_emit_sampler(struct r600_context *rctx,
1958 struct radeon_winsys_cs *cs = rctx->cs;
1997 static void r600_emit_vs_sampler(struct r600_context *rctx, struct r600_atom *atom)
1999 r600_emit_sampler(rctx, &rctx->vs_samplers, 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
2002 static void r600_emit_ps_sampler(struct r600_context *rctx, struct r600_atom *atom)
2004 r600_emit_sampler(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
2007 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
2009 struct radeon_winsys_cs *cs = rctx->cs;
2016 if (!rctx->seamless_cube_map.enabled) {
2022 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2027 r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
2031 void r600_init_state_functions(struct r600_context *rctx)
2033 r600_init_atom(&rctx->seamless_cube_map.atom, r600_emit_seamless_cube_map, 3, 0);
2034 r600_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
2035 r600_init_atom(&rctx->cb_misc_state.atom, r600_emit_cb_misc_state, 0, 0);
2036 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2037 r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0);
2038 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
2039 r600_init_atom(&rctx->vertex_buffer_state.atom, r600_emit_vertex_buffers, 0, 0);
2040 r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffers, 0, 0);
2041 r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffers, 0, 0);
2042 r600_init_atom(&rctx->vs_samplers.views.atom, r600_emit_vs_sampler_views, 0, 0);
2043 r600_init_atom(&rctx->ps_samplers.views.atom, r600_emit_ps_sampler_views, 0, 0);
2047 r600_init_atom(&rctx->vs_samplers.atom_sampler, r600_emit_vs_sampler, 0, EMIT_EARLY);
2048 r600_init_atom(&rctx->ps_samplers.atom_sampler, r600_emit_ps_sampler, 0, EMIT_EARLY);
2050 r600_init_atom(&rctx->sample_mask.atom, r600_emit_sample_mask, 3, 0);
2051 rctx->sample_mask.sample_mask = ~0;
2052 r600_atom_dirty(rctx, &rctx->sample_mask.atom);
2054 rctx->context.create_blend_state = r600_create_blend_state;
2055 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
2056 rctx->context.create_fs_state = r600_create_shader_state_ps;
2057 rctx->context.create_rasterizer_state = r600_create_rs_state;
2058 rctx->context.create_sampler_state = r600_create_sampler_state;
2059 rctx->context.create_sampler_view = r600_create_sampler_view;
2060 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
2061 rctx->context.create_vs_state = r600_create_shader_state_vs;
2062 rctx->context.bind_blend_state = r600_bind_blend_state;
2063 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2064 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
2065 rctx->context.bind_fs_state = r600_bind_ps_shader;
2066 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
2067 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
2068 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
2069 rctx->context.bind_vs_state = r600_bind_vs_shader;
2070 rctx->context.delete_blend_state = r600_delete_state;
2071 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
2072 rctx->context.delete_fs_state = r600_delete_ps_shader;
2073 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
2074 rctx->context.delete_sampler_state = r600_delete_sampler;
2075 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
2076 rctx->context.delete_vs_state = r600_delete_vs_shader;
2077 rctx->context.set_blend_color = r600_set_blend_color;
2078 rctx->context.set_clip_state = r600_set_clip_state;
2079 rctx->context.set_constant_buffer = r600_set_constant_buffer;
2080 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
2081 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
2082 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
2083 rctx->context.set_sample_mask = r600_set_sample_mask;
2084 rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
2085 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
2086 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
2087 rctx->context.set_index_buffer = r600_set_index_buffer;
2088 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
2089 rctx->context.set_viewport_state = r600_set_viewport_state;
2090 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
2091 rctx->context.texture_barrier = r600_texture_barrier;
2092 rctx->context.create_stream_output_target = r600_create_so_target;
2093 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
2094 rctx->context.set_stream_output_targets = r600_set_so_targets;
2098 void r600_adjust_gprs(struct r600_context *rctx)
2101 unsigned num_ps_gprs = rctx->default_ps_gprs;
2102 unsigned num_vs_gprs = rctx->default_vs_gprs;
2110 r600_inval_shader_cache(rctx);
2112 if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs)
2114 diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
2119 if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
2121 diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
2129 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
2133 r600_context_pipe_state_set(rctx, &rstate);
2136 void r600_init_atom_start_cs(struct r600_context *rctx)
2156 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2162 if (rctx->chip_class == R600) {
2171 family = rctx->family;
2290 rctx->default_ps_gprs = num_ps_gprs;
2291 rctx->default_vs_gprs = num_vs_gprs;
2292 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2340 if (rctx->chip_class >= R700) {
2425 if (rctx->chip_class >= R700) {
2450 if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2453 if (rctx->screen->has_streamout) {
2463 struct r600_context *rctx = (struct r600_context *)ctx;
2487 rctx->rasterizer && rctx->rasterizer->flatshade))
2491 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2554 if (rctx->family == CHIP_R600)
2575 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2576 if (rctx->rasterizer)
2577 shader->flatshade = rctx->rasterizer->flatshade;
2582 struct r600_context *rctx = (struct r600_context *)ctx;
2634 struct r600_context *rctx = (struct r600_context *)ctx;
2644 void *r600_create_resolve_blend(struct r600_context *rctx)
2662 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2666 void *r700_create_resolve_blend(struct r600_context *rctx)
2674 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2678 void *r600_create_decompress_blend(struct r600_context *rctx)
2686 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2690 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2695 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2696 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2711 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2714 void r600_update_dual_export_state(struct r600_context * rctx)
2716 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2717 !rctx->ps_shader->current->ps_depth_export;
2718 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2721 if (db_shader_control != rctx->db_shader_control) {
2724 rctx->db_shader_control = db_shader_control;
2727 r600_context_pipe_state_set(rctx, &rstate);