Lines Matching refs:cs
37 struct radeon_winsys_cs *cs = ctx->cs;
70 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 3, 0);
71 cs->buf[cs->cdw++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 +
73 cs->buf[cs->cdw++] = (t[i]->b.buffer_offset +
75 cs->buf[cs->cdw++] = strides[i] >> 2; /* VTX_STRIDE (in DW) */
76 cs->buf[cs->cdw++] = 0; /* BUFFER_BASE */
78 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
79 cs->buf[cs->cdw++] =
85 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
86 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
88 cs->buf[cs->cdw++] = 0; /* unused */
89 cs->buf[cs->cdw++] = 0; /* unused */
90 cs->buf[cs->cdw++] = 0; /* src address lo */
91 cs->buf[cs->cdw++] = 0; /* src address hi */
93 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
94 cs->buf[cs->cdw++] =
99 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
100 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
102 cs->buf[cs->cdw++] = 0; /* unused */
103 cs->buf[cs->cdw++] = 0; /* unused */
104 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
105 cs->buf[cs->cdw++] = 0; /* unused */
114 struct radeon_winsys_cs *cs = ctx->cs;
123 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
124 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
127 cs->buf[cs->cdw++] = 0; /* dst address lo */
128 cs->buf[cs->cdw++] = 0; /* dst address hi */
129 cs->buf[cs->cdw++] = 0; /* unused */
130 cs->buf[cs->cdw++] = 0; /* unused */
132 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
133 cs->buf[cs->cdw++] =
154 uint32_t *ptr = ctx->ws->buffer_map(t[i]->filled_size->cs_buf, ctx->cs, RADEON_USAGE_READ);
162 struct radeon_winsys_cs *cs = ctx->cs;
164 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
165 cs->buf[cs->cdw++] = (R_0084FC_CP_STRMOUT_CNTL - SI_CONFIG_REG_OFFSET) >> 2;
166 cs->buf[cs->cdw++] = 0;
168 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
169 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
171 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
172 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
173 cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2; /* register */
174 cs->buf[cs->cdw++] = 0;
175 cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value */
176 cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* mask */
177 cs->buf[cs->cdw++] = 4; /* poll interval */
182 struct radeon_winsys_cs *cs = ctx->cs;
185 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
186 cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
187 cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(1);
189 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
190 cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
191 cs->buf[cs->cdw++] = S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit);
193 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
194 cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
195 cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(0);
224 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);