Cross Reference: /external/mesa3d/src/mesa/drivers/dri/radeon/radeon

Lines Matching refs:rmesa
96    r100ContextPtr rmesa = (r100ContextPtr)radeon;
99    RADEON_STATECHANGE(rmesa, ctx);
100    if (rmesa->radeon.sarea->tiling_enabled) {
101       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
104       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &=
108    if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
109       sarea->ctx_owner = rmesa->radeon.dri.hwContext;
113 static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
119    r100ContextPtr rmesa = (r100ContextPtr)radeon;
122    rmesa->hw.zbs.dirty = 1;
128    r100ContextPtr rmesa = R100_CONTEXT(ctx);
129    _mesa_vector4f_free( &rmesa->tcl.ObjClean );
176    r100ContextPtr rmesa;
204    rmesa = (r100ContextPtr) CALLOC( sizeof(*rmesa) );
205    if ( !rmesa ) {
210    rmesa->radeon.radeonScreen = screen;
211    r100_init_vtbl(&rmesa->radeon);
220    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
222    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
225    if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
230 	 rmesa->using_hyperz = GL_TRUE;
234       rmesa->texmicrotile = GL_TRUE;
240    radeonInitTextureFuncs( &rmesa->radeon, &functions );
243    if (!radeonInitContext(&rmesa->radeon, &functions,
246      FREE(rmesa);
251    rmesa->radeon.swtcl.RenderIndex = ~0;
252    rmesa->radeon.hw.all_dirty = GL_TRUE;
254    ctx = rmesa->radeon.glCtx;
269    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
277    i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
310    rmesa->boxes = 0;
336       _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
337       _math_matrix_ctr( &rmesa->tmpmat[i] );
338       _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
339       _math_matrix_set_identity( &rmesa->tmpmat[i] );
364    if (rmesa->radeon.glCtx->Mesa_DXTn) {
368    else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
376    radeon_fbo_init(&rmesa->radeon);
380    radeonInitState( rmesa );
383    _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0, 
386    fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
387    rmesa->radeon.iw.irq_seq = -1;
388    rmesa->radeon.irqsEmitted = 0;
389    rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
392    rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
400    tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
401    if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
403       FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
405 	      !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
406       if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
407 	 rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
410       TCL_FALLBACK(rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
413    if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {