Cross Reference: /external/mesa3d/src/mesa/drivers/dri/radeon/radeon_state

Lines Matching refs:hw
512    rmesa->radeon.hw.max_state_size = 0;
516       rmesa->hw.ATOM.cmd_size = SZ;				\
517       rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int));	\
518       rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
519       rmesa->hw.ATOM.name = NM;						\
520       rmesa->hw.ATOM.is_tcl = FLAG;					\
521       rmesa->hw.ATOM.check = check_##CHK;				\
522       rmesa->hw.ATOM.dirty = GL_TRUE;					\
523       rmesa->hw.ATOM.idx = IDX;					\
524       rmesa->radeon.hw.max_state_size += SZ * sizeof(int);		\
533    rmesa->hw.ctx.emit = ctx_emit_cs;
534    rmesa->hw.ctx.check = check_always_ctx;
573       rmesa->hw.tex[i].emit = tex_emit_cs;
579        rmesa->hw.cube[i].emit = cube_emit_cs;
589    rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
590    rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
591    rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
592    rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
593    rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
594    rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
595    rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
596    rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
597    rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL_STATUS);
598    rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
599    rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_0);
600    rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_0);
601    rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_1);
602    rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_1);
603    rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_2);
604    rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_2);
605    rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_0);
606    rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T0);
607    rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_1);
608    rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T1);
609    rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_2);
610    rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T2);
611    rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
612    rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
613    rmesa->hw.mtl.cmd[MTL_CMD_0] = 
615    rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0);
616    rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1);
617    rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2);
618    rmesa->hw.grd.cmd[GRD_CMD_0] = 
620    rmesa->hw.fog.cmd[FOG_CMD_0] = 
622    rmesa->hw.glt.cmd[GLT_CMD_0] = 
624    rmesa->hw.eye.cmd[EYE_CMD_0] = 
628       rmesa->hw.mat[i].cmd[MAT_CMD_0] = 
633       rmesa->hw.lit[i].cmd[LIT_CMD_0] = 
635       rmesa->hw.lit[i].cmd[LIT_CMD_1] = 
640       rmesa->hw.ucp[i].cmd[UCP_CMD_0] = 
644    rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0);
645    rmesa->hw.stp.cmd[STP_DATA_0] = 0;
646    rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31);
648    rmesa->hw.grd.emit = scl_emit;
649    rmesa->hw.fog.emit = vec_emit;
650    rmesa->hw.glt.emit = vec_emit;
651    rmesa->hw.eye.emit = vec_emit;
653       rmesa->hw.mat[i].emit = vec_emit;
656       rmesa->hw.lit[i].emit = lit_emit;
659       rmesa->hw.ucp[i].emit = vec_emit;
665    rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS |
672    rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX |
676    rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
678    rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP |
682    rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (RADEON_Z_TEST_LESS |
690        rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
694 /*	 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
696 	 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY;
700    rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
703    rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
708       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
711       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
721       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
723       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
726    rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
741    rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] =
749      rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
752    rmesa->hw.set.cmd[SET_SE_COORDFMT] = (
757    rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
759    rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] = 
763    rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
765    rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] = 
770    rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY;
771    rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
773    rmesa->hw.msc.cmd[MSC_RE_MISC] = 
778    rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE]  = 0x00000000;
779    rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
780    rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE]  = 0x00000000;
781    rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
782    rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE]  = 0x00000000;
783    rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
786       rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL;
787       rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] = 
795       //      rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
798       rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
799       rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =  
806       rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] = 
813       rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0;
815       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
816       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] =
818       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] =
820       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] =
822       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] =
824       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] =
831    rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = 
837    rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] =
845    rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] = 
849    rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] = 
855    rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = 
859    rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0; 
861    rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = 
873       *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
888       *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
907    rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
908    rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
909    rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
910    rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
912    rmesa->hw.eye.cmd[EYE_X] = 0;
913    rmesa->hw.eye.cmd[EYE_Y] = 0;
914    rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
915    rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
921    rmesa->radeon.hw.all_dirty = GL_TRUE;