Lines Matching refs:env
47 void tlb_flush(CPUArchState *env, int flush_global)
56 env->current_tb = NULL;
62 env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry;
66 memset(env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
68 env->tlb_flush_addr = -1;
69 env->tlb_flush_mask = 0;
85 void tlb_flush_page(CPUArchState *env, target_ulong addr)
94 if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
98 env->tlb_flush_addr, env->tlb_flush_mask);
100 tlb_flush(env, 1);
105 env->current_tb = NULL;
110 tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
113 tb_flush_jmp_cache(env, addr);
127 void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
161 void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
169 tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
175 static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
180 if (env->tlb_flush_addr == (target_ulong)-1) {
181 env->tlb_flush_addr = vaddr & mask;
182 env->tlb_flush_mask = mask;
188 mask &= env->tlb_flush_mask;
189 while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {
192 env->tlb_flush_addr &= mask;
193 env->tlb_flush_mask = mask;
199 void tlb_set_page(CPUArchState *env, target_ulong vaddr,
215 tlb_add_large_page(env, vaddr, size);
260 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
270 env->iotlb[mmu_idx][index] = iotlb - vaddr;
271 te = &env->tlb_table[mmu_idx][index];