Lines Matching refs:env
8 CPUARMState *env = (CPUARMState *)opaque;
11 qemu_put_be32(f, env->regs[i]);
13 qemu_put_be32(f, cpsr_read(env));
14 qemu_put_be32(f, env->spsr);
16 qemu_put_be32(f, env->banked_spsr[i]);
17 qemu_put_be32(f, env->banked_r13[i]);
18 qemu_put_be32(f, env->banked_r14[i]);
21 qemu_put_be32(f, env->usr_regs[i]);
22 qemu_put_be32(f, env->fiq_regs[i]);
24 qemu_put_be32(f, env->cp15.c0_cpuid);
25 qemu_put_be32(f, env->cp15.c0_cachetype);
26 qemu_put_be32(f, env->cp15.c0_cssel);
27 qemu_put_be32(f, env->cp15.c1_sys);
28 qemu_put_be32(f, env->cp15.c1_coproc);
29 qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
30 qemu_put_be32(f, env->cp15.c1_secfg);
31 qemu_put_be32(f, env->cp15.c1_sedbg);
32 qemu_put_be32(f, env->cp15.c1_nseac);
33 qemu_put_be32(f, env->cp15.c2_base0);
34 qemu_put_be32(f, env->cp15.c2_base1);
35 qemu_put_be32(f, env->cp15.c2_control);
36 qemu_put_be32(f, env->cp15.c2_mask);
37 qemu_put_be32(f, env->cp15.c2_base_mask);
38 qemu_put_be32(f, env->cp15.c2_data);
39 qemu_put_be32(f, env->cp15.c2_insn);
40 qemu_put_be32(f, env->cp15.c3);
41 qemu_put_be32(f, env->cp15.c5_insn);
42 qemu_put_be32(f, env->cp15.c5_data);
44 qemu_put_be32(f, env->cp15.c6_region[i]);
46 qemu_put_be32(f, env->cp15.c6_insn);
47 qemu_put_be32(f, env->cp15.c6_data);
48 qemu_put_be32(f, env->cp15.c7_par);
49 qemu_put_be32(f, env->cp15.c9_insn);
50 qemu_put_be32(f, env->cp15.c9_data);
51 qemu_put_be32(f, env->cp15.c9_pmcr);
52 qemu_put_be32(f, env->cp15.c9_pmcnten);
53 qemu_put_be32(f, env->cp15.c9_pmovsr);
54 qemu_put_be32(f, env->cp15.c9_pmxevtyper);
55 qemu_put_be32(f, env->cp15.c9_pmuserenr);
56 qemu_put_be32(f, env->cp15.c9_pminten);
57 qemu_put_be32(f, env->cp15.c13_fcse);
58 qemu_put_be32(f, env->cp15.c13_context);
59 qemu_put_be32(f, env->cp15.c13_tls1);
60 qemu_put_be32(f, env->cp15.c13_tls2);
61 qemu_put_be32(f, env->cp15.c13_tls3);
62 qemu_put_be32(f, env->cp15.c15_cpar);
64 qemu_put_be32(f, env->cp14_dbgdidr);
66 qemu_put_be32(f, env->features);
68 if (arm_feature(env, ARM_FEATURE_VFP)) {
71 u.d = env->vfp.regs[i];
76 qemu_put_be32(f, env->vfp.xregs[i]);
80 qemu_put_be32(f, env->vfp.vec_len);
81 qemu_put_be32(f, env->vfp.vec_stride);
83 if (arm_feature(env, ARM_FEATURE_VFP3)) {
86 u.d = env->vfp.regs[i];
93 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
95 qemu_put_be64(f, env->iwmmxt.regs[i]);
98 qemu_put_be32(f, env->iwmmxt.cregs[i]);
102 if (arm_feature(env, ARM_FEATURE_M)) {
103 qemu_put_be32(f, env->v7m.other_sp);
104 qemu_put_be32(f, env->v7m.vecbase);
105 qemu_put_be32(f, env->v7m.basepri);
106 qemu_put_be32(f, env->v7m.control);
107 qemu_put_be32(f, env->v7m.current_sp);
108 qemu_put_be32(f, env->v7m.exception);
111 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
112 qemu_put_be32(f, env->teecr);
113 qemu_put_be32(f, env->teehbr);
121 CPUARMState *env = (CPUARMState *)opaque;
129 env->regs[i] = qemu_get_be32(f);
133 env->uncached_cpsr = val & CPSR_M;
134 cpsr_write(env, val, 0xffffffff);
135 env->spsr = qemu_get_be32(f);
137 env->banked_spsr[i] = qemu_get_be32(f);
138 env->banked_r13[i] = qemu_get_be32(f);
139 env->banked_r14[i] = qemu_get_be32(f);
142 env->usr_regs[i] = qemu_get_be32(f);
143 env->fiq_regs[i] = qemu_get_be32(f);
145 env->cp15.c0_cpuid = qemu_get_be32(f);
146 env->cp15.c0_cachetype = qemu_get_be32(f);
147 env->cp15.c0_cssel = qemu_get_be32(f);
148 env->cp15.c1_sys = qemu_get_be32(f);
149 env->cp15.c1_coproc = qemu_get_be32(f);
150 env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
151 env->cp15.c1_secfg = qemu_get_be32(f);
152 env->cp15.c1_sedbg = qemu_get_be32(f);
153 env->cp15.c1_nseac = qemu_get_be32(f);
154 env->cp15.c2_base0 = qemu_get_be32(f);
155 env->cp15.c2_base1 = qemu_get_be32(f);
156 env->cp15.c2_control = qemu_get_be32(f);
157 env->cp15.c2_mask = qemu_get_be32(f);
158 env->cp15.c2_base_mask = qemu_get_be32(f);
159 env->cp15.c2_data = qemu_get_be32(f);
160 env->cp15.c2_insn = qemu_get_be32(f);
161 env->cp15.c3 = qemu_get_be32(f);
162 env->cp15.c5_insn = qemu_get_be32(f);
163 env->cp15.c5_data = qemu_get_be32(f);
165 env->cp15.c6_region[i] = qemu_get_be32(f);
167 env->cp15.c6_insn = qemu_get_be32(f);
168 env->cp15.c6_data = qemu_get_be32(f);
169 env->cp15.c7_par = qemu_get_be32(f);
170 env->cp15.c9_insn = qemu_get_be32(f);
171 env->cp15.c9_data = qemu_get_be32(f);
177 env->cp15.c9_pmcr = qemu_get_be32(f);
178 env->cp15.c9_pmcnten = qemu_get_be32(f);
179 env->cp15.c9_pmovsr = qemu_get_be32(f);
180 env->cp15.c9_pmxevtyper = qemu_get_be32(f);
181 env->cp15.c9_pmuserenr = qemu_get_be32(f);
182 env->cp15.c9_pminten = qemu_get_be32(f);
184 env->cp15.c13_fcse = qemu_get_be32(f);
185 env->cp15.c13_context = qemu_get_be32(f);
186 env->cp15.c13_tls1 = qemu_get_be32(f);
187 env->cp15.c13_tls2 = qemu_get_be32(f);
188 env->cp15.c13_tls3 = qemu_get_be32(f);
189 env->cp15.c15_cpar = qemu_get_be32(f);
191 env->cp14_dbgdidr = qemu_get_be32(f);
193 env->features = qemu_get_be32(f);
195 if (arm_feature(env, ARM_FEATURE_VFP)) {
200 env->vfp.regs[i] = u.d;
203 env->vfp.xregs[i] = qemu_get_be32(f);
207 env->vfp.vec_len = qemu_get_be32(f);
208 env->vfp.vec_stride = qemu_get_be32(f);
210 if (arm_feature(env, ARM_FEATURE_VFP3)) {
215 env->vfp.regs[i] = u.d;
220 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
222 env->iwmmxt.regs[i] = qemu_get_be64(f);
225 env->iwmmxt.cregs[i] = qemu_get_be32(f);
229 if (arm_feature(env, ARM_FEATURE_M)) {
230 env->v7m.other_sp = qemu_get_be32(f);
231 env->v7m.vecbase = qemu_get_be32(f);
232 env->v7m.basepri = qemu_get_be32(f);
233 env->v7m.control = qemu_get_be32(f);
234 env->v7m.current_sp = qemu_get_be32(f);
235 env->v7m.exception = qemu_get_be32(f);
238 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
239 env->teecr = qemu_get_be32(f);
240 env->teehbr = qemu_get_be32(f);