Lines Matching defs:in
13 * This library is distributed in the hope that it will be useful,
350 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
743 to r15 in ARM architecture v7 and above. The source must be a temporary
756 * to r15 in ARM architecture v5T and above. This is used for storing
758 * in the ARM ARM which use the LoadWritePC() pseudocode function. */
934 /* Like gen_vfp_mul() but put result in F1 */
945 /* Like gen_vfp_neg() but put result in F1 */
2483 * (a) always UNDEF in usermode
2578 * for things which are real instructions in ARMv7. This allows
2579 * them to work in linux-user mode which doesn't provide functional
2584 /* 0,c7,c0,4: Standard v6 WFI (also used in some pre-v6 cores).
2612 /* 0,c7,c13,1: prefetch-by-MVA in v6, NOP in v7 */
2620 /* Barriers in both v6 and v7 */
2892 /* Not present in VFP3. */
2922 /* Set the 4 flag bits in the CPSR. */
2969 /* The opcode is in bits 23, 21, 20 and 6. */
3004 * in VCVT of fixed to float being the same as that of an SREG_M
3561 mask &= ~CPSR_Q; /* V5TE in reality*/
3580 /* ??? This is also undefined in system mode. */
4436 /* Each entry in this array has bit n set if the insn allows
4489 We process data in a mixture of 32-bit and 64-bit chunks.
4979 element size in bits. */
5064 /* Operands in T0 and T1. */
5168 TCGv_i64 in;
5170 in = cpu_V0;
5172 in = cpu_V1;
5176 gen_helper_neon_rshl_u64(cpu_V0, in, tmp64);
5178 gen_helper_neon_rshl_s64(cpu_V0, in, tmp64);
5182 gen_helper_neon_shl_u64(cpu_V0, in, tmp64);
5184 gen_helper_neon_shl_s64(cpu_V0, in, tmp64);
5433 destinations in problematic ways. */
5584 * the ARM ARM labels bit 24 as Q, but it is in our variable
7303 we never have multiple CPUs running in parallel,
7559 * operation, in which case we must set the Q flag.
7698 goto illegal_op; /* only usable in supervisor mode */
7976 16-bit instructions in case the second half causes an
8096 /* Not available in user mode. */
8195 /* Fault if writeback register is in register list. */
8393 * operation, in which case we must set the Q flag.
8597 /* Implemented as NOP in user mode. */
8664 /* Not accessible in user mode. */
9622 /* base reg not in list: base register writeback */
9625 /* base reg in list: if load, complete it now */
9684 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9742 * bits back to the CPUARMState for every instruction in an IT block. So:
9752 * it because of an exception we know will happen, which is done in
9758 * This is handled in the same way as restoration of the
9759 * PC in these situations: we will be called again with search_pc=1
9760 * and generate a mapping of the condexec bits for each PC in
9766 * we don't need to care about whether CPUARMState is correct in the
9782 /* We always get here via a jump, so know we are not in a
9790 /* We always get here via a jump, so know we are not in a
9907 the TB in the middel of an IT block: