Lines Matching refs:rn
1175 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1177 iwmmxt_store_reg(cpu_M0, rn);
1180 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1182 iwmmxt_load_reg(cpu_M0, rn);
1185 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1187 iwmmxt_load_reg(cpu_V1, rn);
1191 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1193 iwmmxt_load_reg(cpu_V1, rn);
1197 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1199 iwmmxt_load_reg(cpu_V1, rn);
1204 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1206 iwmmxt_load_reg(cpu_V1, rn); \
1211 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1213 iwmmxt_load_reg(cpu_V1, rn); \
1308 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1310 iwmmxt_load_reg(cpu_V1, rn);
2753 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2766 rn = (insn >> 16) & 0xf;
2767 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2768 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
2781 VFP_DREG_N(rn, insn);
2801 tmp = neon_load_reg(rn, pass);
2843 neon_store_reg(rn, n, tmp2);
2845 neon_store_reg(rn, n, tmp);
2850 tmp2 = neon_load_reg(rn, pass);
2855 tmp2 = neon_load_reg(rn, pass);
2862 neon_store_reg(rn, pass, tmp);
2868 rn = VFP_SREG_N(insn);
2873 rn >>= 1;
2875 switch (rn) {
2883 tmp = load_cpu_field(vfp.xregs[rn]);
2888 tmp = load_cpu_field(vfp.xregs[rn]);
2896 tmp = load_cpu_field(vfp.xregs[rn]);
2912 tmp = load_cpu_field(vfp.xregs[rn]);
2918 gen_mov_F0_vreg(0, rn);
2932 rn >>= 1;
2934 switch (rn) {
2951 store_cpu_field(tmp, vfp.xregs[rn]);
2956 store_cpu_field(tmp, vfp.xregs[rn]);
2963 gen_mov_vreg_F0(0, rn);
2973 /* rn is opcode */
2974 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2976 /* rn is register number */
2977 VFP_DREG_N(rn, insn);
2980 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) {
2987 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) {
2996 rn = VFP_SREG_N(insn);
2997 if (op == 15 && rn == 15) {
3010 if (op == 15 && rn > 3)
3046 switch (rn) {
3093 gen_mov_F0_vreg(dp, rn);
3168 switch (rn) {
3292 printf ("rn:%d\n", rn);
3302 if (op == 15 && (rn >= 8 && rn <= 11))
3304 else if (op == 15 && dp && ((rn & 0x1c) == 0x18))
3307 else if (op == 15 && rn == 15)
3338 rn = ((rn + delta_d) & (bank_mask - 1))
3339 | (rn & bank_mask);
3340 gen_mov_F0_vreg(dp, rn);
3354 rn = (insn >> 16) & 0xf;
3370 store_reg(s, rn, tmp);
3377 store_reg(s, rn, tmp);
3385 tmp = load_reg(s, rn);
3392 tmp = load_reg(s, rn);
3399 rn = (insn >> 16) & 0xf;
3409 if (s->thumb && rn == 15) {
3414 addr = load_reg(s, rn);
3443 if (rn == 15 && w) {
3448 if (s->thumb && rn == 15) {
3453 addr = load_reg(s, rn);
3487 store_reg(s, rn, addr);
3905 int rd, rn, rm;
3923 rn = (insn >> 16) & 0xf;
3982 load_reg_var(s, addr, rn);
4062 load_reg_var(s, addr, rn);
4110 base = load_reg(s, rn);
4119 store_reg(s, rn, base);
4496 int rd, rn, rm;
4512 VFP_DREG_N(rn, insn);
4525 if (q && ((rd | rn | rm) & 1)) {
4531 neon_load_reg64(cpu_V0, rn + pass);
4607 rtmp = rn;
4608 rn = rm;
4663 tmp = neon_load_reg(rn, 0);
4664 tmp2 = neon_load_reg(rn, 1);
4671 tmp = neon_load_reg(rn, pass);
5425 if ((src1_wide && (rn & 1)) ||
5437 } else if (rd == rn && !src1_wide) {
5438 tmp = neon_load_reg(rn, 1);
5444 neon_load_reg64(cpu_V0, rn + pass);
5447 if (pass == 1 && rd == rn) {
5450 tmp = neon_load_reg(rn, pass);
5603 if (u && ((rd | rn) & 1)) {
5610 tmp2 = neon_load_reg(rn, pass);
5686 tmp3 = neon_load_reg(rn, 1);
5690 tmp = neon_load_reg(rn, 0);
5739 if (q && ((rd | rn | rm) & 1)) {
5744 neon_load_reg64(cpu_V0, rn);
5746 neon_load_reg64(cpu_V1, rn + 1);
5749 neon_load_reg64(cpu_V0, rn + 1);
5756 neon_load_reg64(cpu_V0, rn);
5757 neon_load_reg64(tmp64, rn + 1);
5759 neon_load_reg64(cpu_V0, rn + 1);
5777 neon_load_reg64(cpu_V0, rn);
6173 if ((rn + n) > 32) {
6187 tmp4 = tcg_const_i32(rn);
6428 /* Load 64-bit value rd:rn. */
6575 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
6715 rn = (insn >> 16) & 0xf;
6716 addr = load_reg(s, rn);
6742 store_reg(s, rn, addr);
6917 rn = (insn >> 16) & 0xf;
6919 tmp2 = load_reg(s, rn);
6950 rn = (insn >> 12) & 0xf;
6966 tmp2 = load_reg(s, rn);
6981 gen_addq(s, tmp64, rn, rd);
6982 gen_storeq_reg(s, rn, rd, tmp64);
6986 tmp2 = load_reg(s, rn);
7034 rn = (insn >> 16) & 0xf;
7035 tmp = load_reg(s, rn);
7189 rn = (insn >> 12) & 0xf;
7203 tmp2 = load_reg(s, rn);
7208 tmp2 = load_reg(s, rn);
7222 gen_addq_lo(s, tmp64, rn);
7224 gen_storeq_reg(s, rn, rd, tmp64);
7238 gen_addq(s, tmp64, rn, rd);
7243 gen_storeq_reg(s, rn, rd, tmp64);
7250 rn = (insn >> 16) & 0xf;
7260 load_reg_var(s, addr, rn);
7305 addr = load_reg(s, rn);
7322 rn = (insn >> 16) & 0xf;
7324 addr = load_reg(s, rn);
7376 store_reg(s, rn, addr);
7380 store_reg(s, rn, addr);
7399 rn = (insn >> 16) & 0xf;
7405 tmp = load_reg(s, rn);
7417 tmp = load_reg(s, rn);
7469 tmp = load_reg(s, rn);
7494 if (rn != 15) {
7495 tmp2 = load_reg(s, rn);
7548 store_reg(s, rn, tmp);
7569 gen_addq(s, tmp64, rd, rn);
7570 gen_storeq_reg(s, rd, rn, tmp64);
7580 store_reg(s, rn, tmp);
7598 store_reg(s, rn, tmp);
7654 rn = (insn >> 16) & 0xf;
7656 tmp2 = load_reg(s, rn);
7677 store_reg(s, rn, tmp2);
7679 store_reg(s, rn, tmp2);
7703 rn = (insn >> 16) & 0xf;
7704 addr = load_reg(s, rn);
7744 } else if (i == rn) {
7792 store_reg(s, rn, addr);
7798 store_reg(s, rn, loaded_var);
7932 uint32_t rd, rn, rm, rs;
7993 rn = (insn >> 16) & 0xf;
8006 if (rn == 15) {
8010 addr = load_reg(s, rn);
8036 if (rn == 15)
8039 store_reg(s, rn, addr);
8046 load_reg_var(s, addr, rn);
8056 if (rn == 15) {
8060 addr = load_reg(s, rn);
8085 load_reg_var(s, addr, rn);
8101 addr = load_reg(s, rn);
8115 store_reg(s, rn, addr);
8153 addr = load_reg(s, rn);
8173 } else if (i == rn) {
8187 store_reg(s, rn, loaded_var);
8196 if (insn & (1 << rn))
8198 store_reg(s, rn, addr);
8210 tmp = load_reg(s, rn);
8232 if (rn == 15) {
8236 tmp = load_reg(s, rn);
8261 tmp = load_reg(s, rn);
8289 if (rn != 15) {
8290 tmp2 = load_reg(s, rn);
8305 tmp = load_reg(s, rn);
8315 tmp = load_reg(s, rn);
8325 tmp = load_reg(s, rn);
8358 tmp = load_reg(s, rn);
8454 tmp = load_reg(s, rn);
8575 tmp = load_reg(s, rn);
8587 tmp = load_reg(s, rn);
8638 tmp = load_reg(s, rn);
8645 if (rn != 14 || rd != 15) {
8648 tmp = load_reg(s, rn);
8704 if (rn == 15) {
8708 tmp = load_reg(s, rn);
8780 if (rn == 15) {
8789 tmp = load_reg(s, rn);
8827 rn = (insn >> 16) & 0xf;
8828 if (rn == 15) {
8832 tmp = load_reg(s, rn);
8880 if (rn == 15) {
8895 if (rn == 15) {
8906 addr = load_reg(s, rn);
8985 store_reg(s, rn, addr);
9001 uint32_t val, insn, op, rm, rn, rd, shift, cond;
9028 rn = (insn >> 3) & 7;
9029 tmp = load_reg(s, rn);
9295 rn = (insn >> 3) & 7;
9298 addr = load_reg(s, rn);
9340 rn = (insn >> 3) & 7;
9341 addr = load_reg(s, rn);
9360 rn = (insn >> 3) & 7;
9361 addr = load_reg(s, rn);
9380 rn = (insn >> 3) & 7;
9381 addr = load_reg(s, rn);
9549 rn = (insn >> 3) & 0x7;
9551 tmp = load_reg(s, rn);
9600 rn = (insn >> 8) & 0x7;
9601 addr = load_reg(s, rn);
9607 if (i == rn) {
9621 if ((insn & (1 << rn)) == 0) {
9623 store_reg(s, rn, addr);
9627 store_reg(s, rn, loaded_var);