Lines Matching refs:env
27 CPUX86State *env = opaque;
33 cpu_synchronize_state(ENV_GET_CPU(env), 0);
36 qemu_put_betls(f, &env->regs[i]);
37 qemu_put_betls(f, &env->eip);
38 qemu_put_betls(f, &env->eflags);
39 hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
43 fpuc = env->fpuc;
44 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
47 fptag |= ((!env->fptags[i]) << i);
62 qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
66 cpu_put_seg(f, &env->segs[i]);
67 cpu_put_seg(f, &env->ldt);
68 cpu_put_seg(f, &env->tr);
69 cpu_put_seg(f, &env->gdt);
70 cpu_put_seg(f, &env->idt);
72 qemu_put_be32s(f, &env->sysenter_cs);
73 qemu_put_betls(f, &env->sysenter_esp);
74 qemu_put_betls(f, &env->sysenter_eip);
76 qemu_put_betls(f, &env->cr[0]);
77 qemu_put_betls(f, &env->cr[2]);
78 qemu_put_betls(f, &env->cr[3]);
79 qemu_put_betls(f, &env->cr[4]);
82 qemu_put_betls(f, &env->dr[i]);
85 a20_mask = (int32_t) env->a20_mask;
89 qemu_put_be32s(f, &env->mxcsr);
91 qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
92 qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
96 qemu_put_be64s(f, &env->efer);
97 qemu_put_be64s(f, &env->star);
98 qemu_put_be64s(f, &env->lstar);
99 qemu_put_be64s(f, &env->cstar);
100 qemu_put_be64s(f, &env->fmask);
101 qemu_put_be64s(f, &env->kernelgsbase);
103 qemu_put_be32s(f, &env->smbase);
105 qemu_put_be64s(f, &env->pat);
106 qemu_put_be32s(f, &env->hflags2);
108 qemu_put_be64s(f, &env->vm_hsave);
109 qemu_put_be64s(f, &env->vm_vmcb);
110 qemu_put_be64s(f, &env->tsc_offset);
111 qemu_put_be64s(f, &env->intercept);
112 qemu_put_be16s(f, &env->intercept_cr_read);
113 qemu_put_be16s(f, &env->intercept_cr_write);
114 qemu_put_be16s(f, &env->intercept_dr_read);
115 qemu_put_be16s(f, &env->intercept_dr_write);
116 qemu_put_be32s(f, &env->intercept_exceptions);
117 qemu_put_8s(f, &env->v_tpr);
121 qemu_put_be64s(f, &env->mtrr_fixed[i]);
122 qemu_put_be64s(f, &env->mtrr_deftype);
124 qemu_put_be64s(f, &env->mtrr_var[i].base);
125 qemu_put_be64s(f, &env->mtrr_var[i].mask);
128 for (i = 0; i < sizeof(env->interrupt_bitmap)/8; i++) {
129 qemu_put_be64s(f, &env->interrupt_bitmap[i]);
131 qemu_put_be64s(f, &env->tsc);
132 qemu_put_be32s(f, &env->mp_state);
135 qemu_put_be64s(f, &env->mcg_cap);
136 if (env->mcg_cap) {
137 qemu_put_be64s(f, &env->mcg_status);
138 qemu_put_be64s(f, &env->mcg_ctl);
139 for (i = 0; i < (env->mcg_cap & 0xff); i++) {
140 qemu_put_be64s(f, &env->mce_banks[4*i]);
141 qemu_put_be64s(f, &env->mce_banks[4*i + 1]);
142 qemu_put_be64s(f, &env->mce_banks[4*i + 2]);
143 qemu_put_be64s(f, &env->mce_banks[4*i + 3]);
150 CPUX86State *env = opaque;
159 qemu_get_betls(f, &env->regs[i]);
160 qemu_get_betls(f, &env->eip);
161 qemu_get_betls(f, &env->eflags);
183 env->fpregs[i].mmx.MMX_Q(0) = mant;
185 env->fpregs[i].d = cpu_set_fp80(mant, exp);
189 env->fpregs[i].mmx.MMX_Q(0) = mant;
196 env->fpuc = fpuc;
198 env->fpstt = (fpus >> 11) & 7;
199 env->fpus = fpus & ~0x3800;
202 env->fptags[i] = (fptag >> i) & 1;
206 cpu_get_seg(f, &env->segs[i]);
207 cpu_get_seg(f, &env->ldt);
208 cpu_get_seg(f, &env->tr);
209 cpu_get_seg(f, &env->gdt);
210 cpu_get_seg(f, &env->idt);
212 qemu_get_be32s(f, &env->sysenter_cs);
214 qemu_get_betls(f, &env->sysenter_esp);
215 qemu_get_betls(f, &env->sysenter_eip);
217 env->sysenter_esp = qemu_get_be32(f);
218 env->sysenter_eip = qemu_get_be32(f);
221 qemu_get_betls(f, &env->cr[0]);
222 qemu_get_betls(f, &env->cr[2]);
223 qemu_get_betls(f, &env->cr[3]);
224 qemu_get_betls(f, &env->cr[4]);
227 qemu_get_betls(f, &env->dr[i]);
228 cpu_breakpoint_remove_all(env, BP_CPU);
229 cpu_watchpoint_remove_all(env, BP_CPU);
231 hw_breakpoint_insert(env, i);
235 env->a20_mask = a20_mask;
237 qemu_get_be32s(f, &env->mxcsr);
239 qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
240 qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
244 qemu_get_be64s(f, &env->efer);
245 qemu_get_be64s(f, &env->star);
246 qemu_get_be64s(f, &env->lstar);
247 qemu_get_be64s(f, &env->cstar);
248 qemu_get_be64s(f, &env->fmask);
249 qemu_get_be64s(f, &env->kernelgsbase);
252 qemu_get_be32s(f, &env->smbase);
255 qemu_get_be64s(f, &env->pat);
256 qemu_get_be32s(f, &env->hflags2);
258 qemu_get_be32s(f, &ENV_GET_CPU(env)->halted);
260 qemu_get_be64s(f, &env->vm_hsave);
261 qemu_get_be64s(f, &env->vm_vmcb);
262 qemu_get_be64s(f, &env->tsc_offset);
263 qemu_get_be64s(f, &env->intercept);
264 qemu_get_be16s(f, &env->intercept_cr_read);
265 qemu_get_be16s(f, &env->intercept_cr_write);
266 qemu_get_be16s(f, &env->intercept_dr_read);
267 qemu_get_be16s(f, &env->intercept_dr_write);
268 qemu_get_be32s(f, &env->intercept_exceptions);
269 qemu_get_8s(f, &env->v_tpr);
275 qemu_get_be64s(f, &env->mtrr_fixed[i]);
276 qemu_get_be64s(f, &env->mtrr_deftype);
278 qemu_get_be64s(f, &env->mtrr_var[i].base);
279 qemu_get_be64s(f, &env->mtrr_var[i].mask);
283 for (i = 0; i < sizeof(env->interrupt_bitmap)/8; i++) {
284 qemu_get_be64s(f, &env->interrupt_bitmap[i]);
286 qemu_get_be64s(f, &env->tsc);
287 qemu_get_be32s(f, &env->mp_state);
291 qemu_get_be64s(f, &env->mcg_cap);
292 if (env->mcg_cap) {
293 qemu_get_be64s(f, &env->mcg_status);
294 qemu_get_be64s(f, &env->mcg_ctl);
295 for (i = 0; i < (env->mcg_cap & 0xff); i++) {
296 qemu_get_be64s(f, &env->mce_banks[4*i]);
297 qemu_get_be64s(f, &env->mce_banks[4*i + 1]);
298 qemu_get_be64s(f, &env->mce_banks[4*i + 2]);
299 qemu_get_be64s(f, &env->mce_banks[4*i + 3]);
307 env->hflags = hflags;
308 tlb_flush(env, 1);
309 cpu_synchronize_state(ENV_GET_CPU(env), 1);