Cross Reference: /external/qemu/target-i386/smm

Lines Matching refs:env
31 void helper_rsm(CPUX86State *env)
43 void do_smm_enter(CPUArchState *env)
50     log_cpu_state_mask(CPU_LOG_INT, ENV_GET_CPU(env), X86_DUMP_CCOP);
52     env->hflags |= HF_SMM_MASK;
53     cpu_smm_update(env);
55     sm_state = env->smbase + 0x8000;
59         dt = &env->segs[i];
67     stq_phys(sm_state + 0x7e68, env->gdt.base);
68     stl_phys(sm_state + 0x7e64, env->gdt.limit);
70     stw_phys(sm_state + 0x7e70, env->ldt.selector);
71     stq_phys(sm_state + 0x7e78, env->ldt.base);
72     stl_phys(sm_state + 0x7e74, env->ldt.limit);
73     stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
75     stq_phys(sm_state + 0x7e88, env->idt.base);
76     stl_phys(sm_state + 0x7e84, env->idt.limit);
78     stw_phys(sm_state + 0x7e90, env->tr.selector);
79     stq_phys(sm_state + 0x7e98, env->tr.base);
80     stl_phys(sm_state + 0x7e94, env->tr.limit);
81     stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
83     stq_phys(sm_state + 0x7ed0, env->efer);
94         stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
95     stq_phys(sm_state + 0x7f78, env->eip);
96     stl_phys(sm_state + 0x7f70, cpu_compute_eflags(env));
97     stl_phys(sm_state + 0x7f68, env->dr[6]);
98     stl_phys(sm_state + 0x7f60, env->dr[7]);
100     stl_phys(sm_state + 0x7f48, env->cr[4]);
101     stl_phys(sm_state + 0x7f50, env->cr[3]);
102     stl_phys(sm_state + 0x7f58, env->cr[0]);
105     stl_phys(sm_state + 0x7f00, env->smbase);
107     stl_phys(sm_state + 0x7ffc, env->cr[0]);
108     stl_phys(sm_state + 0x7ff8, env->cr[3]);
109     stl_phys(sm_state + 0x7ff4, cpu_compute_eflags(env));
110     stl_phys(sm_state + 0x7ff0, env->eip);
119     stl_phys(sm_state + 0x7fcc, env->dr[6]);
120     stl_phys(sm_state + 0x7fc8, env->dr[7]);
122     stl_phys(sm_state + 0x7fc4, env->tr.selector);
123     stl_phys(sm_state + 0x7f64, env->tr.base);
124     stl_phys(sm_state + 0x7f60, env->tr.limit);
125     stl_phys(sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
127     stl_phys(sm_state + 0x7fc0, env->ldt.selector);
128     stl_phys(sm_state + 0x7f80, env->ldt.base);
129     stl_phys(sm_state + 0x7f7c, env->ldt.limit);
130     stl_phys(sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
132     stl_phys(sm_state + 0x7f74, env->gdt.base);
133     stl_phys(sm_state + 0x7f70, env->gdt.limit);
135     stl_phys(sm_state + 0x7f58, env->idt.base);
136     stl_phys(sm_state + 0x7f54, env->idt.limit);
139         dt = &env->segs[i];
149     stl_phys(sm_state + 0x7f14, env->cr[4]);
152     stl_phys(sm_state + 0x7ef8, env->smbase);
157     cpu_load_efer(env, 0);
159     cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
160     env->eip = 0x00008000;
161     cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
163     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0);
164     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, 0);
165     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0);
166     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0);
167     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0);
169     cpu_x86_update_cr0(env,
170                        env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK | CR0_PG_MASK));
171     cpu_x86_update_cr4(env, 0);
172     env->dr[7] = 0x00000400;
176 void helper_rsm(CPUX86State *env)
182     sm_state = env->smbase + 0x8000;
184     cpu_load_efer(env, ldq_phys(sm_state + 0x7ed0));
188         cpu_x86_load_seg_cache(env, i,
195     env->gdt.base = ldq_phys(sm_state + 0x7e68);
196     env->gdt.limit = ldl_phys(sm_state + 0x7e64);
198     env->ldt.selector = lduw_phys(sm_state + 0x7e70);
199     env->ldt.base = ldq_phys(sm_state + 0x7e78);
200     env->ldt.limit = ldl_phys(sm_state + 0x7e74);
201     env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
203     env->idt.base = ldq_phys(sm_state + 0x7e88);
204     env->idt.limit = ldl_phys(sm_state + 0x7e84);
206     env->tr.selector = lduw_phys(sm_state + 0x7e90);
207     env->tr.base = ldq_phys(sm_state + 0x7e98);
208     env->tr.limit = ldl_phys(sm_state + 0x7e94);
209     env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
220         env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
221     env->eip = ldq_phys(sm_state + 0x7f78);
222     cpu_load_eflags(env, ldl_phys(sm_state + 0x7f70),
224     env->dr[6] = ldl_phys(sm_state + 0x7f68);
225     env->dr[7] = ldl_phys(sm_state + 0x7f60);
227     cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48));
228     cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50));
229     cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58));
233         env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff;
236     cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
237     cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
238     cpu_load_eflags(env, ldl_phys(sm_state + 0x7ff4),
240     env->eip = ldl_phys(sm_state + 0x7ff0);
249     env->dr[6] = ldl_phys(sm_state + 0x7fcc);
250     env->dr[7] = ldl_phys(sm_state + 0x7fc8);
252     env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
253     env->tr.base = ldl_phys(sm_state + 0x7f64);
254     env->tr.limit = ldl_phys(sm_state + 0x7f60);
255     env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;
257     env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
258     env->ldt.base = ldl_phys(sm_state + 0x7f80);
259     env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
260     env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;
262     env->gdt.base = ldl_phys(sm_state + 0x7f74);
263     env->gdt.limit = ldl_phys(sm_state + 0x7f70);
265     env->idt.base = ldl_phys(sm_state + 0x7f58);
266     env->idt.limit = ldl_phys(sm_state + 0x7f54);
273         cpu_x86_load_seg_cache(env, i,
279     cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14));
283         env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff;
287     env->hflags &= ~HF_SMM_MASK;
288     cpu_smm_update(env);
291     log_cpu_state_mask(CPU_LOG_INT, ENV_GET_CPU(env), X86_DUMP_CCOP);