Lines Matching refs:env
37 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
46 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
50 if (!(env->CP0_Status & (1 << CP0St_ERL)))
64 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
67 uint8_t ASID = env->CP0_EntryHi & 0xFF;
75 for (i = 0; i < env->tlb->nb_tlb; i++) {
76 tlb = &env->tlb->mmu.r4k.tlb[i];
83 tag &= env->SEGMask;
107 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
112 int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
113 int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
116 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
117 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
118 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
123 qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
128 if (unlikely(env->CP0_Status & (1 << CP0St_ERL))) {
132 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
137 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
138 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
145 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
146 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
153 (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
154 *physical = address & env->PAMask;
162 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
163 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
187 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
195 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
209 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
246 env->CP0_BadVAddr = address;
247 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
249 env->CP0_EntryHi =
250 (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
252 env->CP0_EntryHi &= env->SEGMask;
253 env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
254 ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
255 ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
257 env->exception_index = exception;
258 env->error_code = error_code;
271 static inline target_ulong cpu_mips_get_pgd(CPUMIPSState *env)
306 ebase = env->CP0_EBase - 0x80000000;
322 cpu_abort(env, "TLBMiss handler signature not recognised\n");
332 cpu_abort(env, "pgd_current_p not in KSEG0/KSEG1\n");
345 static inline int cpu_mips_tlb_refill(CPUMIPSState *env, target_ulong address, int rw ,
356 saved_badvaddr = env->CP0_BadVAddr;
357 saved_context = env->CP0_Context;
358 saved_entryhi = env->CP0_EntryHi;
359 saved_hflags = env->hflags;
361 env->CP0_BadVAddr = address;
362 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
364 env->CP0_EntryHi =
365 (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
367 env->hflags = MIPS_HFLAG_KM;
369 fault_addr = env->CP0_BadVAddr;
371 pgd_addr = cpu_mips_get_pgd(env);
387 index = (env->CP0_Context>>1)&0xff8;
395 env->CP0_EntryLo0 = elo_even;
396 env->CP0_EntryLo1 = elo_odd;
398 r4k_helper_ptw_tlbrefill(env);
404 env->hflags = saved_hflags;
406 target_ulong mask = env->CP0_PageMask | ~(TARGET_PAGE_MASK << 1);
422 tlb_set_page(env, address & TARGET_PAGE_MASK,
431 env->CP0_BadVAddr = saved_badvaddr;
432 env->CP0_Context = saved_context;
433 env->CP0_EntryHi = saved_entryhi;
434 env->hflags = saved_hflags;
438 int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
450 log_cpu_state(env, 0);
453 __func__, env->active_tc.PC, address, rw, mmu_idx);
464 ret = get_physical_address(env, &physical, &prot,
469 tlb_set_page(env, address & TARGET_PAGE_MASK,
475 ret = cpu_mips_tlb_refill(env,address,rw,mmu_idx,1);
479 raise_mmu_exception(env, address, rw, ret);
487 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
498 ret = get_physical_address(env, &physical, &prot,
501 raise_mmu_exception(env, address, rw, ret);
509 hwaddr cpu_get_phys_page_debug(CPUMIPSState *env, target_ulong addr)
517 ret = get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT);
519 target_ulong pgd_addr = cpu_mips_get_pgd(env);
587 void do_interrupt (CPUMIPSState *env)
594 if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
595 if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
598 name = excp_names[env->exception_index];
601 __func__, env->active_tc.PC, env->CP0_EPC, name);
603 if (env->exception_index == EXCP_EXT_INTERRUPT &&
604 (env->hflags & MIPS_HFLAG_DM))
605 env->exception_index = EXCP_DINT;
607 switch (env->exception_index) {
609 env->CP0_Debug |= 1 << CP0DB_DSS;
614 env->CP0_DEPC = env->active_tc.PC;
617 env->CP0_Debug |= 1 << CP0DB_DINT;
620 env->CP0_Debug |= 1 << CP0DB_DIB;
623 env->CP0_Debug |= 1 << CP0DB_DBp;
626 env->CP0_Debug |= 1 << CP0DB_DDBS;
629 env->CP0_Debug |= 1 << CP0DB_DDBL;
631 if (env->hflags & MIPS_HFLAG_BMASK) {
634 env->CP0_DEPC = env->active_tc.PC - 4;
635 env->hflags &= ~MIPS_HFLAG_BMASK;
637 env->CP0_DEPC = env->active_tc.PC;
640 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
641 env->hflags &= ~(MIPS_HFLAG_KSU);
643 if (!(env->CP0_Status & (1 << CP0St_EXL)))
644 env->CP0_Cause &= ~(1 << CP0Ca_BD);
645 env->active_tc.PC = (int32_t)0xBFC00480;
648 cpu_reset(ENV_GET_CPU(env));
651 env->CP0_Status |= (1 << CP0St_SR);
652 memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
655 env->CP0_Status |= (1 << CP0St_NMI);
657 if (env->hflags & MIPS_HFLAG_BMASK) {
660 env->CP0_ErrorEPC = env->active_tc.PC - 4;
661 env->hflags &= ~MIPS_HFLAG_BMASK;
663 env->CP0_ErrorEPC = env->active_tc.PC;
665 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
666 env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
667 env->hflags &= ~(MIPS_HFLAG_KSU);
668 if (!(env->CP0_Status & (1 << CP0St_EXL)))
669 env->CP0_Cause &= ~(1 << CP0Ca_BD);
670 env->active_tc.PC = (int32_t)0xBFC00000;
674 if (env->CP0_Cause & (1 << CP0Ca_IV))
682 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
684 int R = env->CP0_BadVAddr >> 62;
685 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
686 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
687 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
698 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
700 int R = env->CP0_BadVAddr >> 62;
701 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
702 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
703 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
735 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
736 (env->error_code << CP0Ca_CE);
765 if (env->CP0_Status & (1 << CP0St_BEV)) {
771 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
772 if (env->hflags & MIPS_HFLAG_BMASK) {
775 env->CP0_EPC = env->active_tc.PC - 4;
776 env->CP0_Cause |= (1 << CP0Ca_BD);
778 env->CP0_EPC = env->active_tc.PC;
779 env->CP0_Cause &= ~(1 << CP0Ca_BD);
781 env->CP0_Status |= (1 << CP0St_EXL);
782 env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
783 env->hflags &= ~(MIPS_HFLAG_KSU);
785 env->hflags &= ~MIPS_HFLAG_BMASK;
786 if (env->CP0_Status & (1 << CP0St_BEV)) {
787 env->active_tc.PC = (int32_t)0xBFC00200;
789 env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
791 env->active_tc.PC += offset;
792 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
795 qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index);
796 printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
799 if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
802 __func__, env->active_tc.PC, env->CP0_EPC, cause,
803 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
804 env->CP0_DEPC);
807 env->exception_index = EXCP_NONE;
810 void r4k_invalidate_tlb (CPUMIPSState *env, int idx)
815 uint8_t ASID = env->CP0_EntryHi & 0xFF;
818 tlb = &env->tlb->mmu.r4k.tlb[idx];
830 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
836 tlb_flush_page (env, addr);
843 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
849 tlb_flush_page (env, addr);