Lines Matching refs:env
30 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
33 static inline void compute_hflags(CPUMIPSState *env)
35 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
38 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
39 !(env->CP0_Status & (1 << CP0St_ERL)) &&
40 !(env->hflags & MIPS_HFLAG_DM)) {
41 env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
44 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
45 (env->CP0_Status & (1 << CP0St_PX)) ||
46 (env->CP0_Status & (1 << CP0St_UX))) {
47 env->hflags |= MIPS_HFLAG_64;
49 if (env->CP0_Status & (1 << CP0St_UX)) {
50 env->hflags |= MIPS_HFLAG_UX;
53 if ((env->CP0_Status & (1 << CP0St_CU0)) ||
54 !(env->hflags & MIPS_HFLAG_KSU)) {
55 env->hflags |= MIPS_HFLAG_CP0;
57 if (env->CP0_Status & (1 << CP0St_CU1)) {
58 env->hflags |= MIPS_HFLAG_FPU;
60 if (env->CP0_Status & (1 << CP0St_FR)) {
61 env->hflags |= MIPS_HFLAG_F64;
63 if (env->insn_flags & ISA_MIPS32R2) {
64 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
65 env->hflags |= MIPS_HFLAG_COP1X;
67 } else if (env->insn_flags & ISA_MIPS32) {
68 if (env->hflags & MIPS_HFLAG_64) {
69 env->hflags |= MIPS_HFLAG_COP1X;
71 } else if (env->insn_flags & ISA_MIPS4) {
76 if (env->CP0_Status & (1 << CP0St_CU3)) {
77 env->hflags |= MIPS_HFLAG_COP1X;
85 void helper_raise_exception_err (CPUMIPSState *env,
92 env->exception_index = exception;
93 env->error_code = error_code;
94 cpu_loop_exit(env);
97 void helper_raise_exception (CPUMIPSState *env, uint32_t exception)
99 helper_raise_exception_err(env, exception, 0);
102 void helper_interrupt_restart (CPUMIPSState *env)
104 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
105 !(env->CP0_Status & (1 << CP0St_ERL)) &&
106 !(env->hflags & MIPS_HFLAG_DM) &&
107 (env->CP0_Status & (1 << CP0St_IE)) &&
108 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
109 env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
110 helper_raise_exception(env, EXCP_EXT_INTERRUPT);
115 static void do_restore_state (CPUMIPSState *env, uintptr_t pc)
121 cpu_restore_state (env, pc);
128 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
131 return (type) cpu_##insn##_raw(env, addr); \
135 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
140 case 0: return (type) cpu_##insn##_kernel(env, addr); break; \
141 case 1: return (type) cpu_##insn##_super(env, addr); break; \
143 case 2: return (type) cpu_##insn##_user(env, addr); break; \
156 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
159 cpu_##insn##_raw(env, addr, val); \
163 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
168 case 0: cpu_##insn##_kernel(env, addr, val); break; \
169 case 1: cpu_##insn##_super(env, addr, val); break; \
171 case 2: cpu_##insn##_user(env, addr, val); break; \
205 static inline uint64_t get_HILO(CPUMIPSState *env)
207 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
210 static inline void set_HILO (CPUMIPSState *env, uint64_t HILO)
212 env->active_tc.LO[0] = (int32_t)HILO;
213 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
216 static inline void set_HIT0_LO (CPUMIPSState *env, target_ulong arg1, uint64_t HILO)
218 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
219 arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
222 static inline void set_HI_LOT0 (CPUMIPSState *env, target_ulong arg1, uint64_t HILO)
224 arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
225 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
229 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
232 set_HI_LOT0(env, arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
237 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
240 set_HI_LOT0(env, arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
245 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
248 set_HI_LOT0(env, arg1, ((int64_t)get_HILO(env)) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
253 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
256 set_HIT0_LO(env, arg1, ((int64_t)get_HILO(env)) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
261 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
264 set_HI_LOT0(env, arg1, ((uint64_t)get_HILO(env)) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
269 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
272 set_HIT0_LO(env, arg1, ((uint64_t)get_HILO(env)) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
277 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
280 set_HI_LOT0(env, arg1, ((int64_t)get_HILO(env)) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
285 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
288 set_HIT0_LO(env, arg1, ((int64_t)get_HILO(env)) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
293 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
296 set_HI_LOT0(env, arg1, ((uint64_t)get_HILO(env)) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
301 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
304 set_HIT0_LO(env, arg1, ((uint64_t)get_HILO(env)) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
309 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
312 set_HIT0_LO(env, arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
317 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
320 set_HIT0_LO(env, arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
325 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
328 set_HIT0_LO(env, arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
333 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
336 set_HIT0_LO(env, arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
342 void helper_dmult (CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
344 muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
347 void helper_dmultu (CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
349 mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
355 static inline hwaddr do_translate_address(CPUMIPSState *env,
361 lladdr = cpu_mips_translate_address(env, address, rw);
364 cpu_loop_exit(env);
371 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
373 env->lladdr = do_translate_address(env, arg, 0); \
375 cpu_single_env->llval = do_##insn(env, arg, mem_idx); \
376 return env->llval; \
385 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
391 env->CP0_BadVAddr = arg2; \
392 helper_raise_exception(env, EXCP_AdES); \
394 if (do_translate_address(env, arg2, 1) == env->lladdr) { \
395 tmp = do_##ld_insn(env, arg2, mem_idx); \
396 if (tmp == env->llval) { \
397 do_##st_insn(env, arg2, arg1, mem_idx); \
418 target_ulong helper_lwl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
423 tmp = do_lbu(env, arg2, mem_idx);
427 tmp = do_lbu(env, GET_OFFSET(arg2, 1), mem_idx);
432 tmp = do_lbu(env, GET_OFFSET(arg2, 2), mem_idx);
437 tmp = do_lbu(env, GET_OFFSET(arg2, 3), mem_idx);
443 target_ulong helper_lwr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
448 tmp = do_lbu(env, arg2, mem_idx);
452 tmp = do_lbu(env, GET_OFFSET(arg2, -1), mem_idx);
457 tmp = do_lbu(env, GET_OFFSET(arg2, -2), mem_idx);
462 tmp = do_lbu(env, GET_OFFSET(arg2, -3), mem_idx);
468 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
471 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
474 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
477 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
480 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
483 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
486 do_sb(env, arg2, (uint8_t)arg1, mem_idx);
489 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
492 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
495 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
508 target_ulong helper_ldl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
513 tmp = do_lbu(env, arg2, mem_idx);
517 tmp = do_lbu(env, GET_OFFSET(arg2, 1), mem_idx);
522 tmp = do_lbu(env, GET_OFFSET(arg2, 2), mem_idx);
527 tmp = do_lbu(env, GET_OFFSET(arg2, 3), mem_idx);
537 tmp = do_lbu(env, GET_OFFSET(arg2, 5), mem_idx);
542 tmp = do_lbu(env, GET_OFFSET(arg2, 6), mem_idx);
547 tmp = do_lbu(env, GET_OFFSET(arg2, 7), mem_idx);
554 target_ulong helper_ldr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
559 tmp = do_lbu(env, arg2, mem_idx);
563 tmp = do_lbu(env, GET_OFFSET(arg2, -1), mem_idx);
568 tmp = do_lbu(env, GET_OFFSET(arg2, -2), mem_idx);
573 tmp = do_lbu(env, GET_OFFSET(arg2, -3), mem_idx);
578 tmp = do_lbu(env, GET_OFFSET(arg2, -4), mem_idx);
583 tmp = do_lbu(env, GET_OFFSET(arg2, -5), mem_idx);
588 tmp = do_lbu(env, GET_OFFSET(arg2, -6), mem_idx);
593 tmp = do_lbu(env, GET_OFFSET(arg2, -7), mem_idx);
600 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
603 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
606 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
609 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
612 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
615 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
618 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
621 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
624 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
627 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
630 do_sb(env, arg2, (uint8_t)arg1, mem_idx);
633 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
636 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
639 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
642 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
645 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
648 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
651 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
663 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
665 int vpe_idx, nr_threads = ENV_GET_CPU(env)->nr_threads;
668 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
670 *tc = env->current_tc;
671 return env;
677 return other ? other->env_ptr : env;
689 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
705 asid = env->CP0_EntryHi & 0xff;
774 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
776 return env->mvp->CP0_MVPControl;
779 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
781 return env->mvp->CP0_MVPConf0;
784 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
786 return env->mvp->CP0_MVPConf1;
789 target_ulong helper_mfc0_random(CPUMIPSState *env)
791 return (int32_t)cpu_mips_get_random(env);
794 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
796 return env->active_tc.CP0_TCStatus;
799 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
801 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
802 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
810 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
812 return env->active_tc.CP0_TCBind;
815 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
817 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
818 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
826 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
828 return env->active_tc.PC;
831 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
833 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
834 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
842 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
844 return env->active_tc.CP0_TCHalt;
847 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
849 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
850 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
858 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
860 return env->active_tc.CP0_TCContext;
863 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
865 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
866 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
874 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
876 return env->active_tc.CP0_TCSchedule;
879 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
881 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
882 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
890 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
892 return env->active_tc.CP0_TCScheFBack;
895 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
897 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
898 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
906 target_ulong helper_mfc0_count(CPUMIPSState *env)
908 return (int32_t)cpu_mips_get_count(env);
911 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
913 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
914 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
919 target_ulong helper_mftc0_status(CPUMIPSState *env)
921 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
922 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
927 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
929 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
932 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
934 return (int32_t)env->CP0_WatchLo[sel];
937 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
939 return env->CP0_WatchHi[sel];
942 target_ulong helper_mfc0_debug(CPUMIPSState *env)
944 target_ulong t0 = env->CP0_Debug;
945 if (env->hflags & MIPS_HFLAG_DM)
951 target_ulong helper_mftc0_debug(CPUMIPSState *env)
953 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
955 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
968 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
970 return env->active_tc.PC;
973 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
975 return env->active_tc.CP0_TCHalt;
978 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
980 return env->active_tc.CP0_TCContext;
983 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
985 return env->active_tc.CP0_TCSchedule;
988 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
990 return env->active_tc.CP0_TCScheFBack;
993 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
995 return env->lladdr >> env->CP0_LLAddr_shift;
998 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
1000 return env->CP0_WatchLo[sel];
1004 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
1007 unsigned int tmp = env->tlb->nb_tlb;
1013 env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
1016 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
1021 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
1024 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1026 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
1030 env->mvp->CP0_MVPControl = newval;
1033 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1040 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1047 env->CP0_VPEControl = newval;
1050 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1055 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1056 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1060 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1064 env->CP0_VPEConf0 = newval;
1067 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1072 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1075 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1082 env->CP0_VPEConf1 = newval;
1085 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1088 env->CP0_YQMask = 0x00000000;
1091 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1093 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1096 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1100 env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1103 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1105 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1108 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1110 env->active_tc.CP0_TCStatus = newval;
1111 sync_c0_tcstatus(env, env->current_tc, newval);
1114 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1116 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1117 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1126 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1131 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1133 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1134 env->active_tc.CP0_TCBind = newval;
1137 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1139 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1142 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1155 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1157 env->active_tc.PC = arg1;
1158 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1159 env->lladdr = 0ULL;
1163 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1165 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1166 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1181 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1183 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1188 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1190 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1191 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1201 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1203 env->active_tc.CP0_TCContext = arg1;
1206 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1208 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1209 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1217 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1219 env->active_tc.CP0_TCSchedule = arg1;
1222 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1224 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1225 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1233 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1235 env->active_tc.CP0_TCScheFBack = arg1;
1238 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1240 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1241 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1249 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1253 env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1256 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1258 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1261 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1264 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1267 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1272 env->CP0_PageGrain = 0;
1275 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1277 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1280 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1282 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1285 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1287 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1290 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1292 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1295 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1297 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1300 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1302 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1305 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1307 env->CP0_HWREna = arg1 & 0x0000000F;
1310 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1312 cpu_mips_store_count(env, arg1);
1315 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1322 val &= env->SEGMask;
1324 old = env->CP0_EntryHi;
1325 env->CP0_EntryHi = val;
1326 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1327 sync_c0_entryhi(env, env->current_tc);
1331 cpu_mips_tlb_flush(env, 1);
1334 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1336 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1337 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1343 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1345 cpu_mips_store_compare(env, arg1);
1348 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1351 uint32_t mask = env->CP0_Status_rw_bitmask;
1354 old = env->CP0_Status;
1355 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1356 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1357 sync_c0_status(env, env, env->current_tc);
1359 compute_hflags(env);
1364 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1365 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1366 env->CP0_Cause);
1367 switch (env->hflags & MIPS_HFLAG_KSU) {
1371 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1374 cpu_mips_update_irq(env);
1377 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1379 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1380 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1383 sync_c0_status(env, other, other_tc);
1386 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1389 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0);
1392 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1395 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1398 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1401 uint32_t old = env->CP0_Cause;
1403 if (env->insn_flags & ISA_MIPS32R2)
1406 env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask);
1408 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1409 if (env->CP0_Cause & (1 << CP0Ca_DC))
1410 cpu_mips_stop_count(env);
1412 cpu_mips_start_count(env);
1418 cpu_mips_update_irq(env);
1422 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1426 env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
1429 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1431 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1434 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1437 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1440 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1442 target_long mask = env->CP0_LLAddr_rw_bitmask;
1443 arg1 = arg1 << env->CP0_LLAddr_shift;
1444 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1447 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1451 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1454 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1456 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1457 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1460 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1462 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1463 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1466 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1468 env->CP0_Framemask = arg1; /* XXX */
1471 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1473 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1475 env->hflags |= MIPS_HFLAG_DM;
1477 env->hflags &= ~MIPS_HFLAG_DM;
1480 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1482 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1484 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1496 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1498 env->CP0_Performance0 = arg1 & 0x000007ff;
1501 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1503 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1506 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1508 env->CP0_DataLo = arg1; /* XXX */
1511 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1513 env->CP0_TagHi = arg1; /* XXX */
1516 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1518 env->CP0_DataHi = arg1; /* XXX */
1522 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1524 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1525 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1533 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1535 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1536 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1544 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1546 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1547 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1555 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1557 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1558 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1566 target_ulong helper_mftdsp(CPUMIPSState *env)
1568 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1569 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1577 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1579 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1580 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1588 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1590 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1591 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1599 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1601 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1602 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1610 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1612 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1613 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1621 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1623 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1624 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1645 target_ulong helper_dvpe(CPUMIPSState *env)
1651 target_ulong helper_evpe(CPUMIPSState *env)
1665 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1672 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1673 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1674 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1675 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1676 helper_raise_exception(env, EXCP_THREAD);
1681 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1682 helper_raise_exception(env, EXCP_THREAD);
1688 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1689 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1690 helper_raise_exception(env, EXCP_THREAD);
1692 return env->CP0_YQMask;
1696 static void inline r4k_invalidate_tlb_shadow (CPUMIPSState *env, int idx)
1699 uint8_t ASID = env->CP0_EntryHi & 0xFF;
1701 tlb = &env->tlb->mmu.r4k.tlb[idx];
1709 static void inline r4k_invalidate_tlb (CPUMIPSState *env, int idx)
1714 uint8_t ASID = env->CP0_EntryHi & 0xFF;
1717 tlb = &env->tlb->mmu.r4k.tlb[idx];
1729 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1735 tlb_flush_page (env, addr);
1742 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1748 tlb_flush_page (env, addr);
1755 void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1758 tlb_flush (env, flush_global);
1761 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1766 tlb = &env->tlb->mmu.r4k.tlb[idx];
1767 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1769 tlb->VPN &= env->SEGMask;
1771 tlb->ASID = env->CP0_EntryHi & 0xFF;
1772 tlb->PageMask = env->CP0_PageMask;
1773 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1774 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1775 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1776 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1777 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1778 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1779 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1780 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1781 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1784 void r4k_helper_ptw_tlbrefill(CPUMIPSState *env)
1787 int r = cpu_mips_get_random(env);
1788 r4k_invalidate_tlb_shadow(env, r);
1789 r4k_fill_tlb(env, r);
1792 void r4k_helper_tlbwi (CPUMIPSState *env)
1802 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
1804 tag = env->CP0_EntryHi & ~mask;
1808 if (tlb->ASID == (env->CP0_EntryHi & 0xFF))
1810 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1811 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1812 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1813 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1814 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1815 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1816 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1817 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1823 cpu_mips_tlb_flush (env, 1);
1825 r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb);
1826 r4k_fill_tlb(env, env->CP0_Index % env->tlb->nb_tlb);
1829 void r4k_helper_tlbwr (CPUMIPSState *env)
1831 int r = cpu_mips_get_random(env);
1833 r4k_invalidate_tlb_shadow(env, r);
1834 r4k_fill_tlb(env, r);
1837 void r4k_helper_tlbp(CPUMIPSState *env)
1846 ASID = env->CP0_EntryHi & 0xFF;
1847 for (i = 0; i < env->tlb->nb_tlb; i++) {
1848 tlb = &env->tlb->mmu.r4k.tlb[i];
1851 tag = env->CP0_EntryHi & ~mask;
1856 env->CP0_Index = i;
1860 if (i == env->tlb->nb_tlb) {
1862 int index = ((env->CP0_EntryHi>>5)&0x1ff00) | ASID;
1863 index |= (env->CP0_EntryHi>>13)&0x20000;
1864 env->CP0_Index |= 0x80000000;
1868 void r4k_helper_tlbr(CPUMIPSState *env)
1873 ASID = env->CP0_EntryHi & 0xFF;
1874 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
1878 cpu_mips_tlb_flush (env, 1);
1881 cpu_mips_tlb_flush (env, 1);
1883 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1884 env->CP0_PageMask = tlb->PageMask;
1885 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1887 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1891 void helper_tlbwi(CPUMIPSState *env)
1893 env->tlb->helper_tlbwi(env);
1896 void helper_tlbwr(CPUMIPSState *env)
1898 env->tlb->helper_tlbwr(env);
1901 void helper_tlbp(CPUMIPSState *env)
1903 env->tlb->helper_tlbp(env);
1906 void helper_tlbr(CPUMIPSState *env)
1908 env->tlb->helper_tlbr(env);
1912 target_ulong helper_di(CPUMIPSState *env)
1914 target_ulong t0 = env->CP0_Status;
1916 env->CP0_Status = t0 & ~(1 << CP0St_IE);
1917 cpu_mips_update_irq(env);
1922 target_ulong helper_ei(CPUMIPSState *env)
1924 target_ulong t0 = env->CP0_Status;
1926 env->CP0_Status = t0 | (1 << CP0St_IE);
1927 cpu_mips_update_irq(env);
1932 static void debug_pre_eret(CPUMIPSState *env)
1936 env->active_tc.PC, env->CP0_EPC);
1937 if (env->CP0_Status & (1 << CP0St_ERL))
1938 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1939 if (env->hflags & MIPS_HFLAG_DM)
1940 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1945 static void debug_post_eret(CPUMIPSState *env)
1949 env->active_tc.PC, env->CP0_EPC);
1950 if (env->CP0_Status & (1 << CP0St_ERL))
1951 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1952 if (env->hflags & MIPS_HFLAG_DM)
1953 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1954 switch (env->hflags & MIPS_HFLAG_KSU) {
1958 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1963 void helper_eret (CPUMIPSState *env)
1965 debug_pre_eret(env);
1966 if (env->CP0_Status & (1 << CP0St_ERL)) {
1967 env->active_tc.PC = env->CP0_ErrorEPC;
1968 env->CP0_Status &= ~(1 << CP0St_ERL);
1970 env->active_tc.PC = env->CP0_EPC;
1971 env->CP0_Status &= ~(1 << CP0St_EXL);
1973 compute_hflags(env);
1974 debug_post_eret(env);
1975 env->lladdr = 1;
1978 void helper_deret (CPUMIPSState *env)
1980 debug_pre_eret(env);
1981 env->active_tc.PC = env->CP0_DEPC;
1982 env->hflags &= MIPS_HFLAG_DM;
1983 compute_hflags(env);
1984 debug_post_eret(env);
1985 env->lladdr = 1;
1989 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
1991 if ((env->hflags & MIPS_HFLAG_CP0) ||
1992 (env->CP0_HWREna & (1 << 0)))
1993 return env->CP0_EBase & 0x3ff;
1995 helper_raise_exception(env, EXCP_RI);
2000 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2002 if ((env->hflags & MIPS_HFLAG_CP0) ||
2003 (env->CP0_HWREna & (1 << 1)))
2004 return env->SYNCI_Step;
2006 helper_raise_exception(env, EXCP_RI);
2011 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2013 if ((env->hflags & MIPS_HFLAG_CP0) ||
2014 (env->CP0_HWREna & (1 << 2)))
2015 return env->CP0_Count;
2017 helper_raise_exception(env, EXCP_RI);
2022 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2024 if ((env->hflags & MIPS_HFLAG_CP0) ||
2025 (env->CP0_HWREna & (1 << 3)))
2026 return env->CCRes;
2028 helper_raise_exception(env, EXCP_RI);
2033 void helper_pmon(CPUMIPSState *env, int function)
2038 if (env->active_tc.gpr[4] == 0)
2039 env->active_tc.gpr[2] = -1;
2042 env->active_tc.gpr[2] = -1;
2046 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2052 unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4];
2059 void helper_wait(CPUMIPSState *env)
2061 ENV_GET_CPU(env)->halted = 1;
2062 helper_raise_exception(env, EXCP_HLT);
2067 static void do_unaligned_access (CPUMIPSState *env,
2086 static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
2089 env->CP0_BadVAddr = addr;
2090 do_restore_state (env, retaddr);
2091 helper_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL);
2094 void tlb_fill (CPUMIPSState* env, target_ulong addr, int is_write, int mmu_idx,
2100 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx);
2108 cpu_restore_state(env, retaddr);
2111 helper_raise_exception_err(env, env->exception_index, env->error_code);
2115 void cpu_unassigned_access(CPUMIPSState* env, hwaddr addr,
2119 helper_raise_exception(env, EXCP_IBE);
2121 helper_raise_exception(env, EXCP_DBE);
2127 static unsigned long v2p_mmu(CPUMIPSState *env, target_ulong addr, int is_user)
2136 tlb_addr = env->tlb_table[is_user][index].addr_read;
2138 physaddr = addr + env->tlb_table[is_user][index].addend;
2142 tlb_fill(env, addr, 0, is_user, retaddr);
2155 CPUMIPSState *env;
2160 env = cpu_single_env;
2163 if (__builtin_expect(env->tlb_table[is_user][index].addr_read !=
2165 physaddr = v2p_mmu(env, addr, is_user);
2167 physaddr = addr + env->tlb_table[is_user][index].addend;
2217 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
2220 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
2222 target_ulong helper_cfc1 (CPUMIPSState *env, uint32_t reg)
2228 arg1 = (int32_t)env->active_fpu.fcr0;
2231 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2234 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2237 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2240 arg1 = (int32_t)env->active_fpu.fcr31;
2247 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg)
2253 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2259 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2264 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2270 env->active_fpu.fcr31 = arg1;
2279 set_float_exception_flags(0, &env->active_fpu.fp_status);
2280 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2281 helper_raise_exception(env, EXCP_FPE);
2302 static inline void update_fcr31(CPUMIPSState *env)
2304 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2306 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2307 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
2308 helper_raise_exception(env, EXCP_FPE);
2310 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2319 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2321 return float64_sqrt(fdt0, &env->active_fpu.fp_status);
2324 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2326 return float32_sqrt(fst0, &env->active_fpu.fp_status);
2329 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2333 set_float_exception_flags(0, &env->active_fpu.fp_status);
2334 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2335 update_fcr31(env);
2339 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2343 set_float_exception_flags(0, &env->active_fpu.fp_status);
2344 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2345 update_fcr31(env);
2349 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2353 set_float_exception_flags(0, &env->active_fpu.fp_status);
2354 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2355 update_fcr31(env);
2359 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2363 set_float_exception_flags(0, &env->active_fpu.fp_status);
2364 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2365 update_fcr31(env);
2366 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2371 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2375 set_float_exception_flags(0, &env->active_fpu.fp_status);
2376 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2377 update_fcr31(env);
2378 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2383 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2388 set_float_exception_flags(0, &env->active_fpu.fp_status);
2389 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2390 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2391 update_fcr31(env);
2395 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2400 set_float_exception_flags(0, &env->active_fpu.fp_status);
2401 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2402 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2403 update_fcr31(env);
2404 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
2411 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2415 set_float_exception_flags(0, &env->active_fpu.fp_status);
2416 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2417 update_fcr31(env);
2421 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2425 set_float_exception_flags(0, &env->active_fpu.fp_status);
2426 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2427 update_fcr31(env);
2431 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2435 set_float_exception_flags(0, &env->active_fpu.fp_status);
2436 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2437 update_fcr31(env);
2441 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2445 set_float_exception_flags(0, &env->active_fpu.fp_status);
2447 update_fcr31(env);
2451 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2455 set_float_exception_flags(0, &env->active_fpu.fp_status);
2457 update_fcr31(env);
2461 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2465 set_float_exception_flags(0, &env->active_fpu.fp_status);
2466 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2467 update_fcr31(env);
2468 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2473 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2477 set_float_exception_flags(0, &env->active_fpu.fp_status);
2478 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2479 update_fcr31(env);
2480 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2485 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2489 set_float_exception_flags(0, &env->active_fpu.fp_status);
2490 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2491 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2493 update_fcr31(env);
2494 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2499 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2503 set_float_exception_flags(0, &env->active_fpu.fp_status);
2504 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2505 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2507 update_fcr31(env);
2508 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2513 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2517 set_float_exception_flags(0, &env->active_fpu.fp_status);
2518 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2519 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2521 update_fcr31(env);
2522 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2527 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2531 set_float_exception_flags(0, &env->active_fpu.fp_status);
2532 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2533 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2535 update_fcr31(env);
2536 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2541 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2545 set_float_exception_flags(0, &env->active_fpu.fp_status);
2546 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2547 update_fcr31(env);
2548 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2553 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2557 set_float_exception_flags(0, &env->active_fpu.fp_status);
2558 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2559 update_fcr31(env);
2560 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2565 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2569 set_float_exception_flags(0, &env->active_fpu.fp_status);
2570 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2571 update_fcr31(env);
2572 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2577 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2581 set_float_exception_flags(0, &env->active_fpu.fp_status);
2582 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2583 update_fcr31(env);
2584 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2589 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2593 set_float_exception_flags(0, &env->active_fpu.fp_status);
2594 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2595 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2597 update_fcr31(env);
2598 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2603 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2607 set_float_exception_flags(0, &env->active_fpu.fp_status);
2608 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2609 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2611 update_fcr31(env);
2612 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2617 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2621 set_float_exception_flags(0, &env->active_fpu.fp_status);
2622 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2623 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2625 update_fcr31(env);
2626 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2631 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2635 set_float_exception_flags(0, &env->active_fpu.fp_status);
2636 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2637 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2639 update_fcr31(env);
2640 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2645 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2649 set_float_exception_flags(0, &env->active_fpu.fp_status);
2650 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2651 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2653 update_fcr31(env);
2654 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2659 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2663 set_float_exception_flags(0, &env->active_fpu.fp_status);
2664 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2665 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2667 update_fcr31(env);
2668 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2673 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2677 set_float_exception_flags(0, &env->active_fpu.fp_status);
2678 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2679 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2681 update_fcr31(env);
2682 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2687 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2691 set_float_exception_flags(0, &env->active_fpu.fp_status);
2692 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2693 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2695 update_fcr31(env);
2696 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2725 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2729 set_float_exception_flags(0, &env->active_fpu.fp_status);
2730 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2731 update_fcr31(env);
2735 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2739 set_float_exception_flags(0, &env->active_fpu.fp_status);
2740 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2741 update_fcr31(env);
2745 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2749 set_float_exception_flags(0, &env->active_fpu.fp_status);
2750 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2751 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2752 update_fcr31(env);
2756 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2760 set_float_exception_flags(0, &env->active_fpu.fp_status);
2761 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2762 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2763 update_fcr31(env);
2767 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2771 set_float_exception_flags(0, &env->active_fpu.fp_status);
2772 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2773 update_fcr31(env);
2777 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2781 set_float_exception_flags(0, &env->active_fpu.fp_status);
2782 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2783 update_fcr31(env);
2787 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2792 set_float_exception_flags(0, &env->active_fpu.fp_status);
2793 fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2794 fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
2795 update_fcr31(env);
2799 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2803 set_float_exception_flags(0, &env->active_fpu.fp_status);
2804 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2805 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2806 update_fcr31(env);
2810 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2814 set_float_exception_flags(0, &env->active_fpu.fp_status);
2815 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2816 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2817 update_fcr31(env);
2821 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2826 set_float_exception_flags(0, &env->active_fpu.fp_status);
2827 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2828 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2829 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2830 fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status);
2831 update_fcr31(env);
2835 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2839 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
2844 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2845 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
2846 update_fcr31(env); \
2847 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
2852 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
2857 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2858 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2859 update_fcr31(env); \
2860 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
2865 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
2876 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2877 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2878 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
2879 update_fcr31(env); \
2880 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \
2895 uint64_t helper_float_ ## name1 ## name2 ## _d(CPUMIPSState *env, \
2899 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2900 return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
2903 uint32_t helper_float_ ## name1 ## name2 ## _s(CPUMIPSState *env, \
2907 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2908 return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2911 uint64_t helper_float_ ## name1 ## name2 ## _ps(CPUMIPSState *env, \
2922 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2923 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2924 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2925 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
2935 uint64_t helper_float_n ## name1 ## name2 ## _d(CPUMIPSState *env, \
2939 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2940 fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
2944 uint32_t helper_float_n ## name1 ## name2 ## _s(CPUMIPSState *env, \
2948 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2949 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2953 uint64_t helper_float_n ## name1 ## name2 ## _ps(CPUMIPSState *env, \
2964 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2965 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2966 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2967 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
2978 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2980 set_float_exception_flags(0, &env->active_fpu.fp_status);
2981 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2982 fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status));
2983 update_fcr31(env);
2987 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2989 set_float_exception_flags(0, &env->active_fpu.fp_status);
2990 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2991 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2992 update_fcr31(env);
2996 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3003 set_float_exception_flags(0, &env->active_fpu.fp_status);
3004 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3005 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3006 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
3007 fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status));
3008 update_fcr31(env);
3012 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3014 set_float_exception_flags(0, &env->active_fpu.fp_status);
3015 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3016 fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status);
3017 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3018 update_fcr31(env);
3022 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3024 set_float_exception_flags(0, &env->active_fpu.fp_status);
3025 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3026 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
3027 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3028 update_fcr31(env);
3032 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3039 set_float_exception_flags(0, &env->active_fpu.fp_status);
3040 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3041 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3042 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
3043 fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status);
3044 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3045 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3046 update_fcr31(env);
3050 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3059 set_float_exception_flags(0, &env->active_fpu.fp_status);
3060 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3061 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3062 update_fcr31(env);
3066 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3075 set_float_exception_flags(0, &env->active_fpu.fp_status);
3076 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3077 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3078 update_fcr31(env);
3084 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3088 update_fcr31(env); \
3090 SET_FP_COND(cc, env->active_fpu); \
3092 CLEAR_FP_COND(cc, env->active_fpu); \
3094 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3101 update_fcr31(env); \
3103 SET_FP_COND(cc, env->active_fpu); \
3105 CLEAR_FP_COND(cc, env->active_fpu); \
3124 FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0))
3125 FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status))
3126 FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3127 FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3128 FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3129 FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3130 FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3131 FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3134 FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0))
3135 FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status))
3136 FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3137 FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3138 FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3139 FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3140 FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3141 FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3144 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3148 update_fcr31(env); \
3150 SET_FP_COND(cc, env->active_fpu); \
3152 CLEAR_FP_COND(cc, env->active_fpu); \
3154 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3161 update_fcr31(env); \
3163 SET_FP_COND(cc, env->active_fpu); \
3165 CLEAR_FP_COND(cc, env->active_fpu); \
3184 FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0))
3185 FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status))
3186 FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3187 FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3188 FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3189 FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3190 FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
3191 FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3194 FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0))
3195 FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status))
3196 FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3197 FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3198 FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3199 FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3200 FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
3201 FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3204 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3214 update_fcr31(env); \
3216 SET_FP_COND(cc, env->active_fpu); \
3218 CLEAR_FP_COND(cc, env->active_fpu); \
3220 SET_FP_COND(cc + 1, env->active_fpu); \
3222 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3224 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3234 update_fcr31(env); \
3236 SET_FP_COND(cc, env->active_fpu); \
3238 CLEAR_FP_COND(cc, env->active_fpu); \
3240 SET_FP_COND(cc + 1, env->active_fpu); \
3242 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3247 FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0),
3248 (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0))
3249 FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status),
3250 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status))
3251 FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3252 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3253 FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3254 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3255 FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3256 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3257 FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3258 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3259 FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
3260 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3261 FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3262 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3265 FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0),
3266 (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0))
3267 FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status),
3268 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status))
3269 FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3270 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3271 FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3272 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3273 FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3274 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3275 FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3276 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3277 FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
3278 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3279 FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3280 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))