Lines Matching refs:szB

948 static IRType preferredVectorSubTypeFromSize ( UInt szB )
950 switch (szB) {
3092 static void gen_narrowing_store ( UInt szB, IRTemp addr, IRExpr* dataE )
3095 switch (szB) {
3116 static IRTemp gen_zwidening_load ( UInt szB, IRTemp addr )
3120 switch (szB) {
3164 UInt szB = 1 << szLg2;
3166 UInt offs = INSN(21,10) * szB;
3174 putIReg64orZR(tt, mkexpr(gen_zwidening_load(szB, ta)));
3176 gen_narrowing_store(szB, ta, getIReg64orZR(tt));
3181 (isLD ? ld_name : st_name)[szLg2], nameIRegOrZR(szB == 8, tt),
3215 UInt szB = 1 << szLg2;
3259 = wBack && simm9 < 0 && szB == 8
3266 putIReg64orZR(tt, mkexpr(gen_zwidening_load(szB, tTA)));
3268 gen_narrowing_store(szB, tTA, getIReg64orZR(tt));
3291 nameIRegOrZR(szB == 8, tt),
3534 UInt szB = 1 << szLg2;
3536 getIReg64orSP(nn), mkU64(imm12 * szB));
3537 switch (szB) {
3542 nameIReg64orSP(nn), imm12 * szB);
3552 nameIReg64orSP(nn), imm12 * szB);
3562 nameIReg64orSP(nn), imm12 * szB);
3768 UInt szB = 4 << szSlg2; /* szB is the per-register size */
3772 simm7 = szB * simm7;
3789 switch (szB) {
3817 if (szB < 16) {
3822 if (szB < 16) {
3826 loadLE(ty, binop(Iop_Add64, mkexpr(tTA), mkU64(szB))));
3830 storeLE(binop(Iop_Add64, mkexpr(tTA), mkU64(szB)),
4124 UInt szB = 4 << INSN(31,30);
4128 IRType ty = preferredVectorSubTypeFromSize(szB);
4459 UInt szB = 1 << szBlg2; /* 1, 2, 4 or 8 */
4460 IRType ty = integerIRTypeOfSize(szB);
4465 /* FIXME generate check that ea is szB-aligned */
4475 nameIRegOrZR(szB == 8, tt), nameIReg64orSP(nn));
4491 nameIRegOrZR(szB == 8, tt), nameIReg64orSP(nn));
4511 UInt szB = 1 << szBlg2; /* 1, 2, 4 or 8 */
4512 IRType ty = integerIRTypeOfSize(szB);
4517 /* FIXME generate check that ea is szB-aligned */
4525 nameIRegOrZR(szB == 8, tt), nameIReg64orSP(nn));
4531 nameIRegOrZR(szB == 8, tt), nameIReg64orSP(nn));