Lines Matching defs:valid
7934 make *u0 and *u1 be valid IRTemps before the call. */
7963 // Can never happen, since VLD2 only has valid lane widths of 32,
7970 *u0 and *u1 be valid IRTemps before the call. */
7999 // Can never happen, since VST2 only has valid lane widths of 32,
8052 make *u0, *u1 and *u2 be valid IRTemps before the call. */
8097 // Can never happen, since VLD3 only has valid lane widths of 32,
8107 make *i0, *i1 and *i2 be valid IRTemps before the call. */
8152 // Can never happen, since VST3 only has valid lane widths of 32,
8162 make *u0, *u1, *u2 and *u3 be valid IRTemps before the call. */
8229 // Can never happen, since VLD4 only has valid lane widths of 32,
8242 make *i0, *i1, *i2 and *i3 be valid IRTemps before the call. */
8310 // Can never happen, since VLD4 only has valid lane widths of 32,
12780 determining whether the masked-out bits are valid for a CP10/11
16058 Bool valid = True;
16068 valid = False;
16072 valid = False;
16074 if (valid) {
16113 Bool valid = True;
16124 valid = False;
16129 valid = False;
16131 if (valid) {
16735 Bool valid = True;
16736 if (rT == 15 || rN == 15 || rN == rT) valid = False;
16737 if (valid) {
16763 Bool valid = True;
16766 valid = False;
16767 if (valid) {
16790 Bool valid = True;
16791 if (rT == 15 || rN == 15 || rN == rT) valid = False;
16792 if (valid) {
16818 Bool valid = True;
16821 valid = False;
16822 if (valid) {
16848 Bool valid = True;
16850 valid = False;
16851 if (valid) {
16875 Bool valid = True;
16877 valid = False;
16878 if (valid) {
16904 Bool valid = True;
16906 valid = False;
16907 if (valid) {
16931 Bool valid = True;
16933 valid = False;
16934 if (valid) {
16960 Bool valid = True;
16962 valid = False;
16963 if (valid) {
16987 Bool valid = True;
16989 valid = False;
16990 if (valid) {
17013 Bool valid = True;
17014 if (rT == 15 || rN == 15 || rN == rT) valid = False;
17015 if (valid) {
17040 Bool valid = True;
17041 if (rT == 15 || rN == 15 || rN == rT || rM == 15) valid = False;
17042 if (valid) {
17067 Bool valid = True;
17068 if (rT == 15 || rN == 15 || rN == rT) valid = False;
17069 if (valid) {
17092 Bool valid = True;
17093 if (rT == 15 || rN == 15 || rN == rT || rM == 15) valid = False;
17094 if (valid) {
17116 Bool valid = True;
17117 if (rN == 15 || rN == rT) valid = False;
17118 if (valid) {
17142 Bool valid = True;
17143 if (rN == 15 || rN == rT || rM == 15) valid = False;
17146 if (valid) {
17577 /* All valid IT instructions must have the form 0xBFxy,
18346 Bool valid = compute_ITSTATE( &newITSTATE, &c1, &c2, &c3,
18348 if (valid && firstcond != 0xF/*NV*/) {
18952 Bool valid = list != 0;
18953 if (valid && 0 != (list & (1 << rN))) {
18956 valid = False;
18959 if (valid) {
19172 Bool valid = True;
19173 if (isBL == 0 && INSN1(0,0) == 1) valid = False;
19174 if (valid) {
19194 valid ARM insn address */
19215 Bool valid = True;
19227 valid = False;
19231 if (rN == 15) valid = False;
19232 if (popcount32(regList) < 2) valid = False;
19233 if (bP == 1 && bM == 1) valid = False;
19234 if (bW == 1 && (regList & (1<<rN))) valid = False;
19237 if (bP == 1) valid = False;
19238 if (rN == 15) valid = False;
19239 if (popcount32(regList) < 2) valid = False;
19240 if (bW == 1 && (regList & (1<<rN))) valid = False;
19243 if (valid) {
19281 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
19283 if (!valid && rD <= 14 && rN == 13)
19284 valid = True;
19285 if (valid) {
19308 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
19310 if (!valid && rD <= 14 && rN == 13)
19311 valid = True;
19312 if (valid) {
19389 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
19392 if (!valid && !isRSB && rN == 13 && rD != 15)
19393 valid = True;
19394 if (valid) {
19423 Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
19425 if (!valid && rD == 13 && rN == 13)
19426 valid = True;
19427 if (valid) {
19562 Bool valid = !isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM);
19565 if (!valid && INSN0(8,5) == BITS4(1,0,0,0) // add
19567 valid = True;
19571 if (!valid && INSN0(8,5) == BITS4(1,1,0,1) // sub
19573 valid = True;
19575 if (valid) {
19772 Bool valid = !isBadRegT(rN) && !isBadRegT(rM) && !isBadRegT(rD);
19773 if (valid) {
19989 Bool valid = True;
20013 valid = False; break;
20024 if (valid) {
20026 valid = False;
20028 valid = False;
20030 valid = False;
20032 valid = False;
20035 valid = False;
20039 valid = False;
20045 if (valid) {
20181 Bool valid = True;
20205 valid = False; break;
20218 valid = False;
20222 valid = False;
20224 valid = False;
20232 if (valid) {
20332 Bool valid = True;
20354 valid = False; break;
20364 valid = False;
20368 if (syned) valid = False;
20370 valid = False;
20382 valid = False;
20386 if (valid) {
20491 Bool valid = True;
20492 if (bP == 0 && bW == 0) valid = False;
20493 if (bW == 1 && (rN == rT || rN == rT2)) valid = False;
20494 if (isBadRegT(rT) || isBadRegT(rT2)) valid = False;
20495 if (bL == 1 && rT == rT2) valid = False;
20499 || bW == 1/*wb*/)) valid = False;
20501 if (valid) {
21558 Bool valid = True;
21559 if (rN == 15 || isBadRegT(rT)) valid = False;
21560 if (valid) {
21581 Bool valid = True;
21582 if (rN == 15 || isBadRegT(rT)) valid = False;
21583 if (valid) {
21602 Bool valid = True;
21603 if (rN == 15 || isBadRegT(rT)) valid = False;
21604 if (valid) {
21622 Bool valid = True;
21627 valid = False;
21631 if (isBadRegT(rT)) valid = False;
21632 if (valid) {
21651 Bool valid = True;
21656 valid = False;
21660 if (isBadRegT(rT)) valid = False;
21661 if (valid) {
21682 Bool valid = True;
21683 if (rN == 15 || isBadRegT(rT)) valid = False;
21684 if (valid) {
21704 Bool valid = True;
21705 if (rN == 15 /* insn is LDRB (literal) */) valid = False;
21706 if (isBadRegT(rT)) valid = False;
21707 if (valid) {
21726 Bool valid = True;
21729 if (rN == 15 /* insn is LDRSB (literal) */) valid = False;
21730 if (isBadRegT(rT)) valid = False;
21731 if (valid) {