Lines Matching refs:vex_state
213 UInt LibVEX_GuestPPC32_get_CR ( /*IN*/const VexGuestPPC32State* vex_state )
217 ( (vex_state->guest_CR##_n##_321 & (7<<1)) \
218 | (vex_state->guest_CR##_n##_0 & 1) \
234 UInt LibVEX_GuestPPC64_get_CR ( /*IN*/const VexGuestPPC64State* vex_state )
238 ( (vex_state->guest_CR##_n##_321 & (7<<1)) \
239 | (vex_state->guest_CR##_n##_0 & 1) \
255 /*OUT*/VexGuestPPC32State* vex_state )
262 vex_state->guest_CR##_n##_0 = toUChar(t & 1); \
263 vex_state->guest_CR##_n##_321 = toUChar(t & (7<<1)); \
282 /*OUT*/VexGuestPPC64State* vex_state )
289 vex_state->guest_CR##_n##_0 = toUChar(t & 1); \
290 vex_state->guest_CR##_n##_321 = toUChar(t & (7<<1)); \
307 UInt LibVEX_GuestPPC32_get_XER ( /*IN*/const VexGuestPPC32State* vex_state )
310 w |= ( ((UInt)vex_state->guest_XER_BC) & 0xFF );
311 w |= ( (((UInt)vex_state->guest_XER_SO) & 0x1) << 31 );
312 w |= ( (((UInt)vex_state->guest_XER_OV) & 0x1) << 30 );
313 w |= ( (((UInt)vex_state->guest_XER_CA) & 0x1) << 29 );
320 UInt LibVEX_GuestPPC64_get_XER ( /*IN*/const VexGuestPPC64State* vex_state )
323 w |= ( ((UInt)vex_state->guest_XER_BC) & 0xFF );
324 w |= ( (((UInt)vex_state->guest_XER_SO) & 0x1) << 31 );
325 w |= ( (((UInt)vex_state->guest_XER_OV) & 0x1) << 30 );
326 w |= ( (((UInt)vex_state->guest_XER_CA) & 0x1) << 29 );
333 /*OUT*/VexGuestPPC32State* vex_state )
335 vex_state->guest_XER_BC = toUChar(xer_native & 0xFF);
336 vex_state->guest_XER_SO = toUChar((xer_native >> 31) & 0x1);
337 vex_state->guest_XER_OV = toUChar((xer_native >> 30) & 0x1);
338 vex_state->guest_XER_CA = toUChar((xer_native >> 29) & 0x1);
344 /*OUT*/VexGuestPPC64State* vex_state )
346 vex_state->guest_XER_BC = toUChar(xer_native & 0xFF);
347 vex_state->guest_XER_SO = toUChar((xer_native >> 31) & 0x1);
348 vex_state->guest_XER_OV = toUChar((xer_native >> 30) & 0x1);
349 vex_state->guest_XER_CA = toUChar((xer_native >> 29) & 0x1);
353 void LibVEX_GuestPPC32_initialise ( /*OUT*/VexGuestPPC32State* vex_state )
356 vex_state->host_EvC_FAILADDR = 0;
357 vex_state->host_EvC_COUNTER = 0;
358 vex_state->pad3 = 0;
359 vex_state->pad4 = 0;
361 vex_state->guest_GPR0 = 0;
362 vex_state->guest_GPR1 = 0;
363 vex_state->guest_GPR2 = 0;
364 vex_state->guest_GPR3 = 0;
365 vex_state->guest_GPR4 = 0;
366 vex_state->guest_GPR5 = 0;
367 vex_state->guest_GPR6 = 0;
368 vex_state->guest_GPR7 = 0;
369 vex_state->guest_GPR8 = 0;
370 vex_state->guest_GPR9 = 0;
371 vex_state->guest_GPR10 = 0;
372 vex_state->guest_GPR11 = 0;
373 vex_state->guest_GPR12 = 0;
374 vex_state->guest_GPR13 = 0;
375 vex_state->guest_GPR14 = 0;
376 vex_state->guest_GPR15 = 0;
377 vex_state->guest_GPR16 = 0;
378 vex_state->guest_GPR17 = 0;
379 vex_state->guest_GPR18 = 0;
380 vex_state->guest_GPR19 = 0;
381 vex_state->guest_GPR20 = 0;
382 vex_state->guest_GPR21 = 0;
383 vex_state->guest_GPR22 = 0;
384 vex_state->guest_GPR23 = 0;
385 vex_state->guest_GPR24 = 0;
386 vex_state->guest_GPR25 = 0;
387 vex_state->guest_GPR26 = 0;
388 vex_state->guest_GPR27 = 0;
389 vex_state->guest_GPR28 = 0;
390 vex_state->guest_GPR29 = 0;
391 vex_state->guest_GPR30 = 0;
392 vex_state->guest_GPR31 = 0;
397 VECZERO(vex_state->guest_VSR0 );
398 VECZERO(vex_state->guest_VSR1 );
399 VECZERO(vex_state->guest_VSR2 );
400 VECZERO(vex_state->guest_VSR3 );
401 VECZERO(vex_state->guest_VSR4 );
402 VECZERO(vex_state->guest_VSR5 );
403 VECZERO(vex_state->guest_VSR6 );
404 VECZERO(vex_state->guest_VSR7 );
405 VECZERO(vex_state->guest_VSR8 );
406 VECZERO(vex_state->guest_VSR9 );
407 VECZERO(vex_state->guest_VSR10);
408 VECZERO(vex_state->guest_VSR11);
409 VECZERO(vex_state->guest_VSR12);
410 VECZERO(vex_state->guest_VSR13);
411 VECZERO(vex_state->guest_VSR14);
412 VECZERO(vex_state->guest_VSR15);
413 VECZERO(vex_state->guest_VSR16);
414 VECZERO(vex_state->guest_VSR17);
415 VECZERO(vex_state->guest_VSR18);
416 VECZERO(vex_state->guest_VSR19);
417 VECZERO(vex_state->guest_VSR20);
418 VECZERO(vex_state->guest_VSR21);
419 VECZERO(vex_state->guest_VSR22);
420 VECZERO(vex_state->guest_VSR23);
421 VECZERO(vex_state->guest_VSR24);
422 VECZERO(vex_state->guest_VSR25);
423 VECZERO(vex_state->guest_VSR26);
424 VECZERO(vex_state->guest_VSR27);
425 VECZERO(vex_state->guest_VSR28);
426 VECZERO(vex_state->guest_VSR29);
427 VECZERO(vex_state->guest_VSR30);
428 VECZERO(vex_state->guest_VSR31);
429 VECZERO(vex_state->guest_VSR32);
430 VECZERO(vex_state->guest_VSR33);
431 VECZERO(vex_state->guest_VSR34);
432 VECZERO(vex_state->guest_VSR35);
433 VECZERO(vex_state->guest_VSR36);
434 VECZERO(vex_state->guest_VSR37);
435 VECZERO(vex_state->guest_VSR38);
436 VECZERO(vex_state->guest_VSR39);
437 VECZERO(vex_state->guest_VSR40);
438 VECZERO(vex_state->guest_VSR41);
439 VECZERO(vex_state->guest_VSR42);
440 VECZERO(vex_state->guest_VSR43);
441 VECZERO(vex_state->guest_VSR44);
442 VECZERO(vex_state->guest_VSR45);
443 VECZERO(vex_state->guest_VSR46);
444 VECZERO(vex_state->guest_VSR47);
445 VECZERO(vex_state->guest_VSR48);
446 VECZERO(vex_state->guest_VSR49);
447 VECZERO(vex_state->guest_VSR50);
448 VECZERO(vex_state->guest_VSR51);
449 VECZERO(vex_state->guest_VSR52);
450 VECZERO(vex_state->guest_VSR53);
451 VECZERO(vex_state->guest_VSR54);
452 VECZERO(vex_state->guest_VSR55);
453 VECZERO(vex_state->guest_VSR56);
454 VECZERO(vex_state->guest_VSR57);
455 VECZERO(vex_state->guest_VSR58);
456 VECZERO(vex_state->guest_VSR59);
457 VECZERO(vex_state->guest_VSR60);
458 VECZERO(vex_state->guest_VSR61);
459 VECZERO(vex_state->guest_VSR62);
460 VECZERO(vex_state->guest_VSR63);
464 vex_state->guest_CIA = 0;
465 vex_state->guest_LR = 0;
466 vex_state->guest_CTR = 0;
468 vex_state->guest_XER_SO = 0;
469 vex_state->guest_XER_OV = 0;
470 vex_state->guest_XER_CA = 0;
471 vex_state->guest_XER_BC = 0;
473 vex_state->guest_CR0_321 = 0;
474 vex_state->guest_CR0_0 = 0;
475 vex_state->guest_CR1_321 = 0;
476 vex_state->guest_CR1_0 = 0;
477 vex_state->guest_CR2_321 = 0;
478 vex_state->guest_CR2_0 = 0;
479 vex_state->guest_CR3_321 = 0;
480 vex_state->guest_CR3_0 = 0;
481 vex_state->guest_CR4_321 = 0;
482 vex_state->guest_CR4_0 = 0;
483 vex_state->guest_CR5_321 = 0;
484 vex_state->guest_CR5_0 = 0;
485 vex_state->guest_CR6_321 = 0;
486 vex_state->guest_CR6_0 = 0;
487 vex_state->guest_CR7_321 = 0;
488 vex_state->guest_CR7_0 = 0;
490 vex_state->guest_FPROUND = PPCrm_NEAREST;
491 vex_state->guest_DFPROUND = PPCrm_NEAREST;
492 vex_state->pad1 = 0;
493 vex_state->pad2 = 0;
495 vex_state->guest_VRSAVE = 0;
497 vex_state->guest_VSCR = 0x0; // Non-Java mode = 0
499 vex_state->guest_EMNOTE = EmNote_NONE;
501 vex_state->guest_CMSTART = 0;
502 vex_state->guest_CMLEN = 0;
504 vex_state->guest_NRADDR = 0;
505 vex_state->guest_NRADDR_GPR2 = 0;
507 vex_state->guest_REDIR_SP = -1;
509 vex_state->guest_REDIR_STACK[i] = 0;
511 vex_state->guest_IP_AT_SYSCALL = 0;
512 vex_state->guest_SPRG3_RO = 0;
514 vex_state->padding1 = 0;
515 vex_state->padding2 = 0;
520 void LibVEX_GuestPPC64_initialise ( /*OUT*/VexGuestPPC64State* vex_state )
523 vex_state->host_EvC_FAILADDR = 0;
524 vex_state->host_EvC_COUNTER = 0;
525 vex_state->pad0 = 0;
526 vex_state->guest_GPR0 = 0;
527 vex_state->guest_GPR1 = 0;
528 vex_state->guest_GPR2 = 0;
529 vex_state->guest_GPR3 = 0;
530 vex_state->guest_GPR4 = 0;
531 vex_state->guest_GPR5 = 0;
532 vex_state->guest_GPR6 = 0;
533 vex_state->guest_GPR7 = 0;
534 vex_state->guest_GPR8 = 0;
535 vex_state->guest_GPR9 = 0;
536 vex_state->guest_GPR10 = 0;
537 vex_state->guest_GPR11 = 0;
538 vex_state->guest_GPR12 = 0;
539 vex_state->guest_GPR13 = 0;
540 vex_state->guest_GPR14 = 0;
541 vex_state->guest_GPR15 = 0;
542 vex_state->guest_GPR16 = 0;
543 vex_state->guest_GPR17 = 0;
544 vex_state->guest_GPR18 = 0;
545 vex_state->guest_GPR19 = 0;
546 vex_state->guest_GPR20 = 0;
547 vex_state->guest_GPR21 = 0;
548 vex_state->guest_GPR22 = 0;
549 vex_state->guest_GPR23 = 0;
550 vex_state->guest_GPR24 = 0;
551 vex_state->guest_GPR25 = 0;
552 vex_state->guest_GPR26 = 0;
553 vex_state->guest_GPR27 = 0;
554 vex_state->guest_GPR28 = 0;
555 vex_state->guest_GPR29 = 0;
556 vex_state->guest_GPR30 = 0;
557 vex_state->guest_GPR31 = 0;
562 VECZERO(vex_state->guest_VSR0 );
563 VECZERO(vex_state->guest_VSR1 );
564 VECZERO(vex_state->guest_VSR2 );
565 VECZERO(vex_state->guest_VSR3 );
566 VECZERO(vex_state->guest_VSR4 );
567 VECZERO(vex_state->guest_VSR5 );
568 VECZERO(vex_state->guest_VSR6 );
569 VECZERO(vex_state->guest_VSR7 );
570 VECZERO(vex_state->guest_VSR8 );
571 VECZERO(vex_state->guest_VSR9 );
572 VECZERO(vex_state->guest_VSR10);
573 VECZERO(vex_state->guest_VSR11);
574 VECZERO(vex_state->guest_VSR12);
575 VECZERO(vex_state->guest_VSR13);
576 VECZERO(vex_state->guest_VSR14);
577 VECZERO(vex_state->guest_VSR15);
578 VECZERO(vex_state->guest_VSR16);
579 VECZERO(vex_state->guest_VSR17);
580 VECZERO(vex_state->guest_VSR18);
581 VECZERO(vex_state->guest_VSR19);
582 VECZERO(vex_state->guest_VSR20);
583 VECZERO(vex_state->guest_VSR21);
584 VECZERO(vex_state->guest_VSR22);
585 VECZERO(vex_state->guest_VSR23);
586 VECZERO(vex_state->guest_VSR24);
587 VECZERO(vex_state->guest_VSR25);
588 VECZERO(vex_state->guest_VSR26);
589 VECZERO(vex_state->guest_VSR27);
590 VECZERO(vex_state->guest_VSR28);
591 VECZERO(vex_state->guest_VSR29);
592 VECZERO(vex_state->guest_VSR30);
593 VECZERO(vex_state->guest_VSR31);
594 VECZERO(vex_state->guest_VSR32);
595 VECZERO(vex_state->guest_VSR33);
596 VECZERO(vex_state->guest_VSR34);
597 VECZERO(vex_state->guest_VSR35);
598 VECZERO(vex_state->guest_VSR36);
599 VECZERO(vex_state->guest_VSR37);
600 VECZERO(vex_state->guest_VSR38);
601 VECZERO(vex_state->guest_VSR39);
602 VECZERO(vex_state->guest_VSR40);
603 VECZERO(vex_state->guest_VSR41);
604 VECZERO(vex_state->guest_VSR42);
605 VECZERO(vex_state->guest_VSR43);
606 VECZERO(vex_state->guest_VSR44);
607 VECZERO(vex_state->guest_VSR45);
608 VECZERO(vex_state->guest_VSR46);
609 VECZERO(vex_state->guest_VSR47);
610 VECZERO(vex_state->guest_VSR48);
611 VECZERO(vex_state->guest_VSR49);
612 VECZERO(vex_state->guest_VSR50);
613 VECZERO(vex_state->guest_VSR51);
614 VECZERO(vex_state->guest_VSR52);
615 VECZERO(vex_state->guest_VSR53);
616 VECZERO(vex_state->guest_VSR54);
617 VECZERO(vex_state->guest_VSR55);
618 VECZERO(vex_state->guest_VSR56);
619 VECZERO(vex_state->guest_VSR57);
620 VECZERO(vex_state->guest_VSR58);
621 VECZERO(vex_state->guest_VSR59);
622 VECZERO(vex_state->guest_VSR60);
623 VECZERO(vex_state->guest_VSR61);
624 VECZERO(vex_state->guest_VSR62);
625 VECZERO(vex_state->guest_VSR63);
629 vex_state->guest_CIA = 0;
630 vex_state->guest_LR = 0;
631 vex_state->guest_CTR = 0;
633 vex_state->guest_XER_SO = 0;
634 vex_state->guest_XER_OV = 0;
635 vex_state->guest_XER_CA = 0;
636 vex_state->guest_XER_BC = 0;
638 vex_state->guest_CR0_321 = 0;
639 vex_state->guest_CR0_0 = 0;
640 vex_state->guest_CR1_321 = 0;
641 vex_state->guest_CR1_0 = 0;
642 vex_state->guest_CR2_321 = 0;
643 vex_state->guest_CR2_0 = 0;
644 vex_state->guest_CR3_321 = 0;
645 vex_state->guest_CR3_0 = 0;
646 vex_state->guest_CR4_321 = 0;
647 vex_state->guest_CR4_0 = 0;
648 vex_state->guest_CR5_321 = 0;
649 vex_state->guest_CR5_0 = 0;
650 vex_state->guest_CR6_321 = 0;
651 vex_state->guest_CR6_0 = 0;
652 vex_state->guest_CR7_321 = 0;
653 vex_state->guest_CR7_0 = 0;
655 vex_state->guest_FPROUND = PPCrm_NEAREST;
656 vex_state->guest_DFPROUND = PPCrm_NEAREST;
657 vex_state->pad1 = 0;
658 vex_state->pad2 = 0;
660 vex_state->guest_VRSAVE = 0;
662 vex_state->guest_VSCR = 0x0; // Non-Java mode = 0
664 vex_state->guest_EMNOTE = EmNote_NONE;
666 vex_state->padding = 0;
668 vex_state->guest_CMSTART = 0;
669 vex_state->guest_CMLEN = 0;
671 vex_state->guest_NRADDR = 0;
672 vex_state->guest_NRADDR_GPR2 = 0;
674 vex_state->guest_REDIR_SP = -1;
676 vex_state->guest_REDIR_STACK[i] = 0;
678 vex_state->guest_IP_AT_SYSCALL = 0;
679 vex_state->guest_SPRG3_RO = 0;
680 vex_state->guest_TFHAR = 0;
681 vex_state->guest_TFIAR = 0;
682 vex_state->guest_TEXASR = 0;